UM0434 datasheet(385/390 Pages) STMICROELECTRONICS

385 / 390 page

Glossary

UM0434

386/391

Page. A region in memory. The OEA defines a page as a 4-Kbyte area of memory, aligned

on a 4-Kbyte boundary.

Page access history bits. The

changed and referenced bits in the PTE keep track of the

access history within the page. The referenced bit is set by the MMU whenever the page is

accessed for a read or write operation. The changed bit is set when the page is stored into.

See

Changed bit and Referenced bit.

Page fault. A page fault is a condition that occurs when the processor attempts to access a

memory location that does not reside within a

page not currently resident in physical

memory. On PowerPC processors, a page fault interrupt condition occurs when a matching,

valid

page table entry (PTE[V] = 1) cannot be located.

Page table. A table in memory is comprised of

page table entries, or PTEs. It is further

organized into eight PTEs per PTEG (page table entry group). The number of PTEGs in the

page table depends on the size of the page table (as specified in the SDR1 register).

Physical memory. Actual memory that can be accessed through system memory bus.

Pipelining. A technique that breaks operations, such as instruction processing or bus

transactions, into smaller distinct stages or tenures (respectively) so that a subsequent

operation can begin before the previous one has completed.

Precise interrupts. A category of interrupt for which the pipeline can be stopped so

instructions that preceded the faulting instruction can complete and subsequent instructions

can be flushed and redispatched after interrupt handling has completed. See

Imprecise

interrupts.

Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction encoding that

identifies the type of instruction.

Program order. The order of instructions in an executing program. More specifically, this

term is used to refer to the original order in which program instructions are fetched into the

instruction queue from the cache.

Protection boundary. A boundary between

protection domains.

Quiesce. To come to rest. The processor is said to quiesce when an interrupt is taken or a

sync instruction is executed. The instruction stream is stopped at the decode stage and

executing instructions are allowed to complete to create a controlled context for instructions

that may be affected by out-of-order, parallel execution. See

Context synchronization.

Quiet NaN. A type of

NaN that can propagate through most arithmetic operations without

signaling interrupts. A quiet NaN is used to represent the results of certain invalid

operations, such as invalid arithmetic operations on infinities or on NaNs, when invalid. See

Signaling NaN.

Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set, updates the

condition register (CR) to reflect the result of the operation.

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