UM0434 datasheet(382/390 Pages) STMICROELECTRONICS

382 / 390 page

UM0434

Glossary

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Effective address (EA). The 32-bit address specified for a load, store, or an instruction

fetch. This address is then submitted to the MMU for translation to either a

physical memory

address or an I/O address.

Exception. A condition that, if enabled, generates an interrupt.

Execution synchronization. A mechanism by which all instructions in execution are

architecturally complete before beginning execution (appearing to begin execution) of the

next instruction. Similar to context synchronization but doesn't force the contents of the

instruction buffers to be deleted and refetched.

Exponent. In the binary representation of a floating-point number, the exponent is the

component that normally signifies the integer power to which the value two is raised in

determining the value of the represented number. See also

Biased exponent.

Fall-through (branch fall-through). A not-taken branch.

Fetch. Retrieving instructions from either the cache or main memory and placing them into

the instruction queue.

Finish. Finishing occurs in the last cycle of execution. In this cycle, the CQ entry is updated

to indicate that the instruction has finished executing.

Flush. An operation that causes a cache block to be invalidated and the data, if modified, to

be written to memory.

Fraction. In the binary representation of a floating-point number, the field of the

significand

that lies to the right of its implied binary point.

General-purpose register (GPR). Any of the 32 registers in the general-purpose register

file. These registers provide the source operands and destination results for all integer data

manipulation instructions. Integer load instructions move data from memory to GPRs and

store instructions move data from GPRs to memory.

Guarded. The guarded attribute pertains to out-of-order execution. When a page is

designated as guarded, instructions and data cannot be accessed out-of-order.

Harvard architecture. An architectural model featuring separate caches and other memory

management resources for instructions and data.

Hashing. An algorithm used in the

page table search process.

IEEE 754. A standard written by the Institute of Electrical and Electronics Engineers that

defines operations and representations of binary floating-point numbers.

Illegal instructions. A class of instructions that are not implemented for a particular

PowerPC processor. These include instructions not defined by the PowerPC architecture. In

UM0434 Datasheet(PDF) 382 Page - STMicroelectronics