UM0434 datasheet(378/390 Pages) STMICROELECTRONICS

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UM0434

Nexus3 module

379/391

T0, A0 and S0 are the least significant bits, where Tx = TCODE number (fixed); Sx = source processor (fixed); Zx = data size

(fixed); Ax = unique portion of address (variable); Dx = Write data (variable-8,16 or 32-bit).

12.15

IEEE 1149.1 (JTAG) RD/WR sequences

This section contains examples of JTAG/OnCE sequences used to access resources.

12.15.1

JTAG sequence for accessing internal nexus registers

Table 281 shows the JTAG/OnCE sequence for accessing internal Nexus3 registers.

12.15.2

JTAG sequence for read access of Memory-Mapped resources

Table 282 shows the JTAG sequence for read-accessing memory-mapped resources.

T5T4T3

T2T1T0

Start message

End packet

D7D6

D5D4D3

D2D1D0

End packet/end message

Table 280.

Data write message example (8 MDO/2 MSEO) (continued)

Clock

nex_mdo[7:0]

nex_mseo_b[1:0]

State

Table 281.

Accessing internal Nexus3 registers through JTAG/OnCE

Step

TMS pin

Description

IDLE—SELECT–DR_SCAN

SELECT–DR_SCAN—CAPTURE-DR (Nexus command register value loaded in shifter)

CAPTURE-DR—SHIFT-DR

(7) TCK clocks issued to shift in direction (RD/WR) bit and first 6 bits of Nexus register

address

SHIFT-DR—EXIT1–DR (7th bit of Nexus reg. shifted in)

EXIT1-DR—UPDATE-DR (Nexus shifter is transferred to Nexus command register)

UPDATE-DR—SELECT-DR_SCAN

SELECT-DR_SCAN—CAPTURE-DR (Register value is transferred to Nexus shifter)

CAPTURE-DR—SHIFT-DR

(31) TCK clocks issued to transfer register value to TDO pin while shifting in TDI value

SHIFT-DR—EXIT1–DR (MSB of value is shifted in/out of shifter)

EXIT1-DR—UPDATE–DR (if access is write, shifter is transferred to register)

UPDATE-DR—RUN-TEST/IDLE (transfer complete–Nexus controller to register select

state)

Table 282.

Accessing memory-mapped resources (reads)

Step

TCLK clocks

Description

Nexus command = write to read/write access address register (RWA)

Write RWA (initialize starting read address–data input on TDI)

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