UM0434 datasheet(381/390 Pages) STMICROELECTRONICS

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Glossary

UM0434

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Cache. High-speed memory containing recently accessed data or instructions (subset of

main memory).

Cache block. A small region of contiguous memory that is copied from memory into a

cache. The size of a cache block may vary among processors; the maximum block size is

one

page. In PowerPC processors, cache coherency is maintained on a cache-block basis.

Note that the term

cache block is often used interchangeably with ‘cache line.’

Cache coherency. An attribute wherein an accurate and common view of memory is

provided to all devices that share the same memory system. Caches are coherent if a

processor performing a read from its cache is supplied with data corresponding to the most

recent value written to memory or to another processor’s cache.

Cache flush. An operation that removes from a cache any data from a specified address

range. This operation ensures that any modified data within the specified address range is

written back to main memory. This operation is generated typically by a Data Cache Block

Flush (dcbf) instruction.

Caching-inhibited. A memory update policy in which the cache is bypassed and the load

or store is performed to or from main memory.

Cast out. A

cache block that must be written to memory when a cache miss causes a

cache block to be replaced.

Changed bit. One of two

page history bits found in each page table entry (PTE). The

processor sets the changed bit if any store is performed into the

page. See also Page

access history bits and Referenced bit.

Clean. An operation that causes a

cache block to be written to memory, if modified, and

then left in a valid, unmodified state in the cache.

Clear. To cause a bit or bit field to register a value of zero. See also

Set.

Completion. Completion occurs when an instruction has finished executing, written back

any results, and is removed from the completion queue (CQ). When an instruction

completes, it is guaranteed that this instruction and all previous instructions can cause no

interrupts.

Context synchronization. An operation that ensures that all instructions in execution

complete past the point where they can produce an

interrupt, that all instructions in

execution complete in the context in which they began execution, and that all subsequent

instructions are

fetched and executed in the new context. Context synchronization may

result from executing specific instructions (such as isync or rfi) or when certain events

occur (such as an

interrupt).

Copy-back operation. A cache operation in which a cache line is copied back to memory

to enforce cache coherency. Copy-back operations consist of snoop push-out operations

and cache cast-out operations.

Denormalized number. A nonzero floating-point number whose exponent has a reserved

value, usually the format's minimum, and whose explicit or implicit leading significand bit is

zero.

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