AM3874 datasheet(35/361 Pages) TI

35 / 361 page

AM3874, AM3871

www.ti.com

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

3.2.1

Boot Configuration

Table 3-1. Boot Configuration Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

MUXED

DESCRIPTION

NAME

NO.

BOOT

GPMC CS0 default GPMC_Wait enable input. This pin is

multiplexed between ARM Cortex-A8 boot mode and

General-Purpose Memory Controller (GPMC) peripheral

functions. At reset, BTMODE[15] is sampled to determine

GPMC

the GPMC CS0 Wait enable:

GPMC_D[15]/

DIS

Y25

PINCNTL104

BTMODE[15]

DVDD_GPMC

•

0 = Wait disabled

DSIS: PIN

•

1 = Wait enabled

After reset, this pin functions as GPMC multiplexed

data/address pin 15 (GPMC_D[15]).

GPMC

GPMC CS0 default Address/Data multiplexing mode

GPMC_D[14]/

DIS

V24

PINCNTL103

input. These pins are multiplexed between ARM Cortex-

BTMODE[14]

DVDD_GPMC

DSIS: PIN

A8 boot mode and General-Purpose Memory Controller

(GPMC) peripheral functions. At reset, BTMODE[14:13]

are sampled to determine the GPMC CS0 Address/Data

multiplexing:

•

00 = Not muxed

GPMC

GPMC_D[13]/

DIS

•

01 = A/A/D muxed

U23

PINCNTL102

BTMODE[13]

DVDD_GPMC

•

10 = A/D muxed

DSIS: PIN

•

11 = Reserved

After reset, this pin functions as GPMC multiplexed

data/address pins 14 through 13 (GPMC_D[14:13]).

GPMC CS0 default Data Bus Width input. This pin is

multiplexed between ARM Cortex-A8 boot mode and

General-Purpose Memory Controller (GPMC) peripheral

functions. At reset, BTMODE[12] is sampled to determine

GPMC

the GPMC CS0 bus width:

GPMC_D[12]/

DIS

U24

PINCNTL101

BTMODE[12]

DVDD_GPMC

•

0 = 8-bit data bus

DSIS: PIN

•

1 = 16-bit data bus

After reset, this pin functions as GPMC multiplexed

data/address pin 12 (GPMC_D[12]).

RSTOUT_WD_OUT Configuration. This pin is

multiplexed between ARM Cortex-A8 boot mode and

General-Purpose Memory Controller (GPMC) peripheral

functions. At reset, BTMODE[11] is sampled to determine

the function of the RSTOUT_WD_OUT pin:

GPMC

•

0 = RSTOUT is asserted when a Watchdog Timer

GPMC_D[11]/

DIS

AA27

PINCNTL100

reset, POR, RESET, or Emulation/Software-Global

BTMODE[11]

DVDD_GPMC

DSIS: PIN

Cold/Warm reset occurs

•

1 = RSTOUT_WD_OUT is asserted only when a

Watchdog Timer reset occurs

After reset, this pin functions as GPMC multiplexed

data/address pin 11 (GPMC_D[11]).

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-

selected Input State

(2)

IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.

(3)

Specifies the operating I/O supply voltage for each signal

Device Pins

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