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AM3874 Datasheet(PDF) 99 Page - Texas Instruments

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Part # AM3874
Description  AM387x Sitara??ARM Processors
PDF  361 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3874 Datasheet(HTML) 99 Page - Texas Instruments

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AM3874, AM3871
www.ti.com
SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013
3.2.14 Reset, Interrupts, and JTAG Interface
Table 3-25. RESET, Interrupts, and JTAG Terminal Functions
SIGNAL
TYPE(1)
OTHER(2) (3)
MUXED
DESCRIPTION
NAME
NO.
RESET
IPU
–
RESET
J5
I
Device Reset input
DVDD
PINCNTL260
–
POR
F1
I
–
Power-On Reset input
DVDD
Reset output (RSTOUT) or watchdog out (WD_OUT)
DIS
–
RSTOUT_WD_OUT
K6
O
For more detailed information on RSTOUT_WD_OUT pin
DVDD
PINCNTL262
behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.
INTERRUPTS
IPU
–
NMI
H7
I
Non-Maskable Interrupt input
DVDD
PINCNTL261
Interrupt-capable general-purpose I/Os.
see
see
see
NOTE: All pins are multiplexed with other pin functions.
GP0[31:0]
I/O
Table 3-10
NOTE
Table 3-10
See Table 3-10, GP0 Terminal Functions table for muxing
and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see
see
see
NOTE: All pins are multiplexed with other pin functions.
GP1[31:0]
I/O
Table 3-11
NOTE
Table 3-11
See Table 3-11, GP1 Terminal Functions table for muxing
and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see
see
see
NOTE: All pins are multiplexed with other pin functions.
GP2[31:0]
I/O
Table 3-12
NOTE
Table 3-12
See Table 3-12, GP2 Terminal Functions table for muxing
and internal pullup/pulldown/disable details.
Interrupt-capable general-purpose I/Os.
see
see
see
NOTE: All pins are multiplexed with other pin functions.
GP3[31:0]
I/O
Table 3-13
NOTE
Table 3-13
See Table 3-13, GP3 Terminal Functions table for muxing
and internal pullup/pulldown/disable details.
JTAG
IPU
TCLK
W7
I
–
JTAG test clock input
DVDD
JTAG return clock output
IPU/DIS
The internal pullup (IPU) is enabled for this pin when the
RTCK
AD4
O
–
DVDD
device is in reset and the IPU is disabled (DIS) when reset
is released.
IPU
TDI
Y7
I
–
JTAG test data input
DVDD
IPU
TDO
AC5
O
–
JTAG test port data output
DVDD
IPU
JTAG test port mode select input. For proper operation, do
TMS
AA7
I
–
DVDD
not oppose the IPU on this pin.
IPD
TRST
AA4
I
–
JTAG test port reset input
DVDD
VOUT[0],
VOUT[0]_R_CR[2]/
IPD
GP2
EMU4/
AD9
I/O
Emulator pin 4
DVDD
PINCNTL196
GP2[26]
DSIS: PIN
VOUT[0],
VOUT[0]_G_Y_YC[2]/
IPD
GP2
EMU3/
AH7
I/O
Emulator pin 3
DVDD
PINCNTL188
GP2[24]
DSIS: PIN
(1)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2)
IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.
(3)
Specifies the operating I/O supply voltage for each signal
Copyright © 2011–2013, Texas Instruments Incorporated
Device Pins
99
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Product Folder Links: AM3874 AM3871



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