AM3874 datasheet(98/361 Pages) TI

98 / 361 page

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

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3.2.13 PCI Express (PCIe)

Table 3-24. PCI Express (PCIe) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

PCIE_TXP0

AD2

PCIE Transmit Data Lane 0.

–

When the PCIe SERDES are powered down, these pins should be

VDDA_PCIE_1P8

PCIE_TXN0

AD1

left unconnected.

PCIE_RXP0

AC2

PCIE Receive Data Lane 0.

–

When the PCIe SERDES are powered down, these pins should be

VDDA_PCIE_1P8

PCIE_RXN0

AC1

left unconnected.

–

PCIE Serdes Reference Clock Inputs and optional SATA

SERDES_CLKP

AF1

SERDES_CLK LDO

Reference Clock Inputs.

(internal)

Shared between PCI Express and Serial ATA. When PCI Express

–

is not used, and these pins are not used as optional SATA

SERDES_CLKN

AF2

SERDES_CLK LDO

Reference Clock Inputs, these pins can be left unconnected.

(internal)

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-

selected Input State

(2)

IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown

resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.

(3)

Specifies the operating I/O supply voltage for each signal

Device Pins

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