AM3874 datasheet(91/361 Pages) TI

91 / 361 page

AM3874, AM3871

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SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

Table 3-18. McASP1 Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

MUXED

DESCRIPTION

NAME

NO.

McASP1

MCA[1]

MCA[1]_ACLKR/

IPD

I/O

PINCNTL33

McASP1 Receive Bit Clock I/O

MCA[1]_AXR[4]

DVDD

DSIS: 0

MCA[1]

MCA[1]_AFSR/

IPD

I/O

PINCNTL34

McASP1 Receive Frame Sync I/O

MCA[1]_AXR[5]

DVDD

DSIS: 0

IPD

–

MCA[1]_ACLKX

I/O

McASP1 Transmit Bit Clock I/O

DVDD

PINCNTL31

AUD_CLKIN1/

AUD_CLKIN1,

MCA[0]_AXR[8]/

MCA[0], MCA[4],

MCA[1]_AHCLKX/

IPD

EDMA, TIMER2,

MCA[4]_AHCLKX/

I/O

McASP1 Transmit High-Frequency Master Clock I/O

DVDD

GP0

EDMA_EVT3/

PINCNTL15

TIM2_IO/

DSIS: PIN

GP0[8]

IPD

–

MCA[1]_AFSX

I/O

McASP1 Transmit Frame Sync I/O

DVDD

PINCNTL32

MCA[3]

MCA[3]_AXR[3]/

IPD

PINCNTL50

I/O

MCA[1]_AXR[9]/

DVDD

DSIS: PIN

MM: MUX1

MCA[0]

MCA[0]_AXR[5]/

IPD

PINCNTL26

I/O

MCA[1]_AXR[9]

DVDD

DSIS: PIN

MM: MUX0

MCA[3], GP0

MCA[3]_AXR[2]/

IPD

PINCNTL49

MCA[1]_AXR[8]/

I/O

DVDD

DSIS: PIN

GP0[20]

MM: MUX1

MCA[0]

MCA[0]_AXR[4]/

IPD

PINCNTL25

I/O

MCA[1]_AXR[8]

DVDD

DSIS: PIN

MM: MUX0

MCA[2]_AXR[3]/

MCA[2], TIMER3,

MCA[1]_AXR[7]/

IPD

GP0

I/O

McASP1 Transmit/Receive Data I/Os

TIM3_IO/

DVDD

PINCNTL44

GP0[15]

DSIS: PIN

MCA[2]_AXR[2]/

MCA[2], TIMER2,

MCA[1]_AXR[6]/

IPD

GP0

I/O

TIM2_IO/

DVDD

PINCNTL43

GP0[14]

DSIS: PIN

MCA[1]

MCA[1]_AFSR/

IPD

I/O

PINCNTL34

MCA[1]_AXR[5]

DVDD

DSIS: PIN

MCA[1]

MCA[1]_ACLKR/

IPD

I/O

PINCNTL33

MCA[1]_AXR[4]

DVDD

DSIS: PIN

MCB

MCA[1]_AXR[3]/

IPD

I/O

PINCNTL38

MCB_CLKR

DVDD

DSIS: PIN

MCB

MCA[1]_AXR[2]/

IPD

I/O

PINCNTL37

MCB_FSR

DVDD

DSIS: PIN

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-

selected Input State

(2)

IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.

(3)

Specifies the operating I/O supply voltage for each signal

Device Pins

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