AM3874 datasheet(7/361 Pages) TI

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AM3874, AM3871

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SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPRS695B device-specific

data manual to make it an SPRS695C revision.

Scope: Applicable updates to the AM387x Sitara™ ARM Processor device family, specifically relating to

the AM3874/1 devices (Silicon Revisions 3.0, 2.1), which are now in the production data (PD) stage of

development have been incorporated.

•

Updated/Changed Power-Up Sequence

•

Updated/Changed Power-Down Sequence

•

Low-end OPP combinations no longer supported (CVDD_x < CVDD)

•

Added RXACTIVE Function (Bit 18) to PINCTRLx Register Description

•

Added Power-On Hours (POH) section

•

Added Latch-Up Performance Absolute Maximum Ratings

•

DDR2/DDR3 supports up to 533 MHz

•

OPP50 is not supported

•

SmartReflex™ (AVS) is not supported

•

Deep Sleep Mode is not supported

•

HDMI HDCP encryption is not supported

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

•

Replaced all instances of "DSP/EDMA MMU" with "System MMU"

Global

•

Deleted all references to OPP50 and Deep Sleep Mode

•

Deleted the AM3872 device along with any device-specific information; no longer supported

•

Updated/Changed description the HD Video Processing Subsystem (HDVPSS)

Section 1

•

Updated/Changed the Dual 32-Bit DDR2/DDR3 SDRAM Interfaces sub-bullet from "Supports up to

Features

DDR2-800 and DDR3-800" to "Supports up to DDR2-800 and DDR3-1066"

Table 2-2, Characteristics of the Processor:

Section 2.2

•

Updated/Changed the HD Video Processing Subsystem (HDVPSS) row

Device Characteristics

•

Updated/Changed Core Logic (V), OPP100, OPP120 range from "0.95 V – 1.20 V" to "1.10 V –

1.20 V"

Table 2-5, L4 Slow Peripheral Memory Map:

Section 2.9.2.2

L4 Slow Peripheral

•

Updated/Changed 0x4818_8000–0x4818_BFFF Device Name from "SmartReflex0/1 Peripheral

Memory Map

and Support Registers" to "Reserved"

Table 3-11, GP1 Terminal Functions:

Section 3.2.7

General-Purpose

•

Added "The ENLVCMOS bit in the MLBP_DAT_IO_CTRL register...." to the pin descriptions for

Input/Outputs (GPIOs)

pins GP1[10:7] (V2, V1, W2, and W1 respectively).

Table 3-48, Reserved Terminal Functions:

Section 3.2.25

Reserved Pins

•

Updated/Changed TYPE for Signal No. Y14 (RSV4) and AC8 (RSV5) from "S" to "I"

Section 4.3, Pin Multiplexing Control:

•

Updated/Changed bit 18 from "RSV" to "RXACTIVE"

Table 4-11, PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions:

•

Updated/Changed the MUXMODE[7:0] Description from "Values other than those ..." to "A value

of zero results ..."

•

Updated/Changed bit 18 description to now support RXACTIVE

Section 4

Device Configurations

Table 4-13, PINCNTLx Registers MUXMODE Functions:

•

Updated/Changed PINCNTL173 row under 0x20 from "UART2_TXD(M1)" to "UART2_TXD(M0)"

•

Updated/Changed PINCNTL231 under 0x80 from "GP3[30](M0)" to "GP3[30](M1)"

Section 4.4, Handling Unused Pins:

•

Added "Unless otherwise noted" to the beginning of, "All supply pins must always ..."

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