AM3874 datasheet(102/361 Pages) TI

102 / 361 page

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

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3.2.16 SD Signals (MMC/SD/SDIO)

Table 3-27. SD0 Terminal Functions

SIGNAL

OTHER(2)

TYPE(1)

MUXED

DESCRIPTION

(3)

NAME

NO.

GP0

SD0_CLK/

IPU

PINCNTL8

SD0 Clock output

GP0[1]

DVDD_SD

DSIS: 1

SD0_CMD/

SD1, GP0

IPU

SD1_CMD/

I/O

PINCNTL9

SD0 Command input/output

DVDD_SD

GP0[2]

DSIS: 1

SD0_DAT[0]/

SD1, GP0

IPU

SD0 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD mode

SD1_DAT[4]/

I/O

PINCNTL10

DVDD_SD

and single data bit for 1-bit SD mode.

GP0[3]

DSIS: PIN

SD0_DAT[1]_SDIRQ/

SD1, GP0

IPU

SD0 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD mode

SD1_DAT[5]/

I/O

PINCNTL11

DVDD_SD

and as an IRQ input for 1-bit SD mode.

GP0[4]

DSIS: PIN

SD0_DAT[2]_SDRW/

SD1, GP0

IPU

SD0 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD mode

SD1_DAT[6]/

I/O

PINCNTL12

DVDD_SD

and as a Read Wait input for 1-bit SD mode.

GP0[5]

DSIS: PIN

SD0_DAT[3]/

SD1, GP0

IPU

SD1_DAT[7]/

I/O

PINCNTL13

SD0 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD mode.

DVDD_SD

GP0[6]

DSIS: PIN

MCA[1]

MCA[1]_AXR[0]/

IPU

I/O

PINCNTL35

SD0 Data4 I/O. Functions as data bit 4 for 8-bit SD mode.

SD0_DAT[4]/

DVDD

DSIS: PIN

MCA[1], SC0

MCA[1]_AXR[1]/

IPU

I/O

PINCNTL36

SD0 Data5 I/O. Functions as data bit 5 for 8-bit SD mode.

SD0_DAT[5]/

DVDD

DSIS: PIN

MCA[2]_AXR[0]/

MCA[2], UART5,

SD0_DAT[6]/

IPU

GP0

I/O

SD0 Data6 I/O. Functions as data bit 6 for 8-bit SD mode.

UART5_RXD/

DVDD

PINCNTL41

GP0[12]

DSIS: PIN

MCA[2]_AXR[1]/

MCA[2], UART5,

SD0_DAT[7]/

IPU

GP0

I/O

SD0 Data7 I/O. Functions as data bit 7 for 8-bit SD mode.

UART5_TXD/

DVDD

PINCNTL42

GP0[13]

DSIS: PIN

UART0_CTS/

UART0, UART4,

UART4_RXD/

IPD

DCAN1, SPI[1]

DCAN1_TX/

AE6

SD0 Card Detect input

DVDD

PINCNTL72

SPI[1]_SCS[3]/

DSIS: 1

SD0_SDCD

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-

selected Input State

(2)

IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown

resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and Section 7.3.17, Pin Behaviors at Reset.

(3)

Specifies the operating I/O supply voltage for each signal

102

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