ADP5080 datasheet(36/64 Pages) AD

36 / 64 page

ADP5080

Data Sheet

Table 14. Minimum Recommended Output Capacitors

Channel

Output Capacitor (µF)

Ceramic capacitors are manufactured with a variety of dielectrics,

each with different behavior over temperature and applied voltage.

Capacitors must have a dielectric that is adequate to ensure the

minimum capacitance over the necessary temperature range and

dc bias conditions. X5R or X7R dielectrics with a voltage rating

of at least 2 × VOUT are recommended for best performance.

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using Equation 5.

VRIPPLE =

OUT

RIPPLE

OUT

)

(

(5)

High ESR capacitors are not recommended because they increase

output ripple and can cause loop instability. Equation 5 assumes

ceramic capacitors and does not include ESR.

For optimal performance, place output capacitors to minimize

PCB parasitics. Connect capacitor pads directly to the output

and GND power paths, not via separate traces. For purposes of

high frequency noise reduction, it can be beneficial to use multiple

capacitors in parallel instead of a single high value capacitor.

Because Channel 6 operates in buck boost mode, the output

capacitors see large switching currents. Therefore, placement of

the output capacitors requires additional attention. Make sure

to place the output capacitors as close as possible to the VOUT6

and PGND6 pins of Channel 6.

COMPONENT SELECTION FOR THE LDO

REGULATORS

Selecting the Capacitors

Use low ESR capacitors for all LDO input and output capacitors.

Lower ESR reduces the output impedance and ripple voltage.

High ESR capacitors are not recommended due to ripple and

stability of the LDO control loop. Therefore, it is recommended

that surface-mount ceramic capacitors be used. The X5R and

X7R type of capacitor is preferable for adequate performance.

Use an output capacitor with a value from 2.2 µF to 10 µF

for VREG2. Values of 4.7 µF to 10 µF are recommended for

VREG1; 4.7 µF is the minimum requirement for stability.

For the Channel 7 high voltage LDO regulator, the minimum

required output capacitor value for the VOLDO7 pin is 1 µF.

Because Channel 7 is a high voltage output, make sure to account

for capacitor bias voltage derating. If the charge pump doubler

circuit is used as the input supply to Channel 7, the maximum

recommended value for the Channel 7 output capacitor is 3.3 µF.

This is to prevent overloading the charge pump during startup.

PCB LAYOUT RECOMMENDATIONS

Proper printed circuit board (PCB) layout is essential for optimal

device performance and thermal dissipation, and to minimize

switching noise and electromagnetic interference (EMI). A few

key layout guidelines are provided in the following sections.

Sensitive Signal Treatment

It is important to isolate sensitive signal traces from noisy

switching traces. The FBx pins and the FREQ pin are sensitive

to noise coupling and should be routed away from noise sources.

Any node with high dV/dt—such as SWx, BSTx, and SCL—is

considered a noise source.

Additional noisy circuit areas to avoid are the main areas of high

switching current: primarily the input capacitors and PGNDx

connections. Finally, do not route sensitive nodes below or near

the inductors. If a sensitive signal trace must cross a noisy source,

it is recommended that at least one PCB ground layer be placed

between these signal traces as a shield.

Grounding

It is recommended that the analog ground (AGND) and power

ground (PGND) planes be separated. The AGND plane is used

for the device reference voltage; therefore, it should be as quiet as

possible and not used as a current path. The PGND plane serves

as the current return path for the regulators. PGND can be very

noisy due to the flow of current, as well as the presence of switch-

ing noise. Therefore, care must be taken with the connection

of the AGND and PGND planes so that currents flowing in the

PGND plane do not intrude on the AGND region. Connect the

AGND and PGND planes at a single point, preferably at the device.

The PGNDx nodes are part of the regulation loop for each

switching regulator and carry fast switching currents. Therefore,

it is critical that the PGNDx regions for each switching regulator

be separated and connected to the PGND plane at the output

capacitor ground. This prevents interference from adjacent

channels and helps contain switching noise. Multiple vias are

recommended for the connection between the PGNDx regions

and the PGND plane.

To improve thermal performance and noise immunity, each

AGND or PGND layer should have as much copper coverage

as possible.

Rev. A | Page 36 of 64

ADP5080 Datasheet(PDF) 36 Page - Analog Devices

ADP5080 Datasheet(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL