ADP5080 datasheet(25/64 Pages) AD

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Data Sheet

ADP5080

Rev. A | Page 25 of 64

Current-Limit Protection, Channel 4 and Channel 5

Channel 4 and Channel 5 have integrated cycle-by-cycle current-

limit protection. In this type of current-limit protection, inductor

current is sensed throughout the high-side on cycle. If the

inductor current rises above the current-limit threshold during

this time, the switching pulse is immediately terminated until

the next cycle. This behavior causes the duty cycle to decrease,

which in turn causes the output voltage to fall. The falling output

voltage then toggles the PWRGx, UVx, and FAULT error flags.

Because there is substantial parasitic noise at the rising edge of

the high-side switch, some blanking time is required to prevent

false current-limit triggering. This required blanking time

determines the minimum on time of the channel.

Unlike valley mode current-limit protection, peak mode current-

limit protection has no inherent frequency foldback. In extreme

conditions such as a short circuit or inductor saturation, peak

mode current limit is susceptible to runaway inductor current.

To prevent this, the ADP5080 provides frequency foldback on

Channel 4, Channel 5, and Channel 6. When the output voltage

falls below approximately 80% of its nominal value, the switch-

ing frequency is halved. The frequency is halved again if the output

voltage falls below approximately 40% of its nominal value. The

frequency foldback feature allows more time for inductor current

to decay, eliminating the possibility of current runaway.

Table 3 provides the peak current-limit threshold specifications.

The actual load current-limit threshold varies with inductor

value, frequency, and input and output voltage.

Discharge Switch, Channel 4 and Channel 5

Each channel incorporates a discharge switch. For Channel 4, the

discharge switch is located at the SW4 pin; for Channel 5, the

discharge switch is located at the FB5 pin. The discharge switch

can be turned on when the corresponding channel output is turned

off, removing the residual charge of the external capacitor via a

125 Ω resistor. The discharge switch can be enabled by setting the

appropriate DSCGx_ON bit in Register 1.

Channel 6: Buck or Buck Boost Regulator

Channel 6 is a current mode control, four-switch buck boost

regulator that can be configured as a buck only regulator. In a

system in which the input voltage never falls below the Channel 6

output, using the buck only configuration reduces the losses

caused by the switching FETs of the boost side. The buck only

configuration yields better power efficiency, as well as lower

output ripple and noise.

Buck Only Configuration

For the buck only configuration, set the BUCK6_ONLY bit (Bit 4

in Register 30) to 1. The default value of this bit is factory fuse

programmed. When Channel 6 is configured for buck only mode,

connect the inductor between the SW6A and VOUT6 pins, leaving

the SW6B pin open (see Figure 42). This configuration bypasses

the boost side switching FET.

Buck Boost Configuration

For the buck boost configuration, set the BUCK6_ONLY bit

(Bit 4 in Register 30) to 0. The default value of this bit is factory

fuse programmed. For the buck boost configuration, connect

the inductor between the SW6A and SW6B pins (see Figure 42).

Make sure that no capacitor is connected to the SW6B pin.

In buck boost operation, Channel 6 automatically switches

between the buck and boost modes as the input voltage varies.



In buck mode, the primary FETs (SW6A) switch with the

SW6B high-side FET operating at 100% duty cycle.



In boost mode, all four FETs are typically switching, although

the primary high-side FET is capable of a 100% duty cycle.

When the input voltage is close to the output voltage, Channel 6

operates in buck boost mode with all four power FETs switching.

This four-switch mode of operation ensures a smooth transition

and excellent regulation, regardless of input voltage conditions.

The BOOST6_VTH bits (Bits[1:0] in Register 30) set the input

voltage threshold for the boost FETs to start switching. A lower

threshold provides higher efficiency because the region where

all four switches are in operation is smaller. The lowest setting

for these bits (11) sets an input voltage threshold that is still high

enough to prevent dropout in most cases. However, under heavy

load current at the lowest threshold setting, the buck side may

reach a 100% duty cycle and some output droop may occur. The

second lowest setting for these bits (00) is recommended for heavy

load applications. The default value of these bits is factory fuse

programmed.

Selecting the Output Voltage, Channel 6

The output voltage of Channel 6 is selected from one of the

preset values available in the VID6 bits (see Table 45). The

default output voltage value is factory fuse programmed.

Channel 6 has an adjustable mode option that can be selected

using the VID6 bits. When the adjustable output voltage mode

is selected, the output voltage is set by an external feedback

resistor divider. Select resistor values such that the desired output

voltage is divided down to 0.8 V while the paralleled resistance seen

from the dividing node does not exceed 25 kΩ (see the Setting

the Output Voltage (Adjustable Mode Channels) section).

Because Channel 6 can operate in boost mode, there is no practical

output voltage limitation other than the maximum rating. When

using the adjustable output voltage in buck only mode, be aware

of the minimum on time restriction, which may limit the range

of available output voltages. The minimum on time limitation is

essentially the same as for Channel 4 and Channel 5 (see the

Selecting the Output Voltage, Channel 4 and Channel 5 section).

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