ADP5080 datasheet(29/64 Pages) AD

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Data Sheet

ADP5080

SOFT START FUNCTION

To provide controlled output voltage ramping on startup, the

ADP5080 incorporates soft start control for each dc-to-dc con-

verter. The ramp-up period to reach the target voltage can be

set to 1 ms, 2 ms, 4 ms, or 8 ms using the SSx bit (where x is 1

to 6) in Register 2 or Register 3. The default soft start values

are factory fuse programmed. It is not recommended that the

ADP5080 be started up into a full load condition.

CHANNEL 7: HIGH VOLTAGE LDO REGULATOR

The ADP5080 integrates a high voltage LDO linear regulator,

which allows input voltages up to 25 V (see Figure 47). The

LDO regulator outputs one of four preset regulated voltages

and is capable of providing up to 30 mA.

Figure 47. High Voltage LDO (Channel 7)

Selecting the Output Voltage, Channel 7

The output voltage of Channel 7 is selected from one of the

preset values (12 V, 9 V, 6 V, or 5 V) using the VID7 bits in

Discharge Switch, Channel 7

Each channel incorporates a discharge switch. For Channel 7,

the discharge switch is located at the VOLDO7 pin. The dis-

charge switch can be turned on when Channel 7 is turned off,

removing the residual charge of the external capacitor via an

internal 1 kΩ resistor. The discharge switch can be enabled by

setting the DSCG7_ON bit in Register 1.

CHARGE PUMP

The ADP5080 includes an integrated charge pump, which

provides power to the high-side switching NMOS FET driver

(see Figure 48). The charge pump raises the voltage applied to

the PVINCP pin by the VDR5 pin voltage, making the voltage

available at the BSTCP pin. In a typical application, the PVINCP

pin is supplied by the battery (VBATT), and the VDR5 pin is

supplied by VREG1 (5 V or 5.5 V). Thus, the output voltage at

the BSTCP pin is VBATT + 5 V or 5.5 V, which is ideal for driving

the high-side FET driver supply pin for each channel, BSTx.

Figure 48. Charge Pump for BSTx Supply

The charge pump requires a minimum VBATT voltage to start

up. In some cases, the start-up threshold, which is 4 V typical,

may be higher than the rising UVLO threshold.

If the BSTCP voltage drops approximately 2.5 V below the

nominal value, the ADP5080 shuts down to prevent abnormal

switching. An OVP or UVP fault is not indicated in this case.

Charge Pump Switching Frequency

The internal clock source generates either 2.0 MHz or 1.5 MHz,

as set by the SEL_FSW bit in Register 18. This master frequency

is further divided by 1/2, 1/4, 1/8, or 1/16 by the FREQ_CP bits

in Register 19 (see Table 53). If the master clock frequency is set

to 2.0 MHz, the charge pump switching clock frequency can be

1.0 MHz, 500 kHz, 250 kHz, or 125 kHz. If the master frequency

is set to 1.5 MHz, the charge pump switching clock frequency can

be 750 kHz, 375 kHz, 188 kHz, or 94 kHz. Typically, a setting of

1/4 in 1.5 MHz operation or 1/8 in 2 MHz operation is recom-

mended for the best efficiency. Lower settings may not provide

enough boost voltage when all channels are operating at load.

If an external clock is used, the charge pump frequency can be set

to 1/4 or 1/8 of the external frequency using the FREQ_CP bits.

Charge pump efficiency is slightly affected by the duty cycle of the

external clock; a 50% duty cycle is the optimal point of operation.

Capacitor Selection

A 1 µF capacitor is used for each charge pump capacitor (CFLY

and COUT; see Figure 48). The voltage rating of these capacitors

must be adequate for the charge-up voltage, that is, the PVINCP

pin voltage across CFLY and the VDR5 pin voltage across COUT.

Protection Diode

It is strongly recommended that a protection diode be mounted

as shown in Figure 48 to avoid problems during power-up while

the BSTCP voltage is charging. Use a Schottky diode that can

withstand a 1 A peak current.

PROGRAMMABLE

SOFT START

POWER-GOOD

COMPARATOR

UVP

VREF

SEQUENCER

DISCHARGE

SWITCH

ADP5080

CURRENT

LIMIT

CURRENT

DETECTION

AGND

VILDO7

VOLDO7

UP TO

25V

5V TO 12V

AGND

C+

C–

PGND5

PVINCP

BSTCP

VDR5

CLOCK

CFLY

1µF

COUT

1µF

OUTPUT

VVBATT + VVDR5

VBATT

BSTx

Rev. A | Page 29 of 64

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