ADP5080 datasheet(19/64 Pages) AD

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Data Sheet

ADP5080

THEORY OF OPERATION

The ADP5080 is a fully integrated, high efficiency power solu-

tion for multicell lithium ion battery applications. The device

can connect directly to the battery, which eliminates the need

for preregulators and increases the battery life of the system.

The ADP5080 integrates two keep-alive LDO regulators, five

synchronous buck regulators, one configurable buck boost regu-

lator, and one high voltage LDO regulator. An integrated charge

pump provides the switch driver power supply. Along with the

integrated power FETs and drivers, integrated compensation,

soft start, and FB dividers contribute to minimize the number

of external components and the PCB layout space, providing

significant advantages for portable applications.

Factory programming sets the default values for the output

voltages, fault behavior, switching frequency, start-up time, and

other functions. These values can also be programmed via the

I2C interface. The ADP5080 features a built-in sequencer that

provides automatic startup and shutdown timing based on these

settings.

UVLO AND POR

The undervoltage lockout (UVLO) and power-on reset (POR)

functions prevent abnormal behavior and force a smooth shut-

down when input voltages fall below the minimum required

levels. The ADP5080 incorporates UVLO on VBATT, PVIN1,

and VDR12; it incorporates POR on VREG2. The thresholds

are low enough to ensure normal operation down to 4 V at

VBATT with ample hysteresis to avoid chattering.

Undervoltage Lockout (UVLO)

If the PVIN1 voltage of Channel 1 falls below the UVLO threshold

(VUVLO (F)), all channels, as well as the charge pump, are turned

off. However, LDO1 and LDO2 remain operational.

As the input voltage rises, the regulator channels do not restart

automatically. EN must be toggled after a UVLO event to restart

channels in sequencer mode or manual mode. For more informa-

tion about enabling channels using sequencer mode and manual

mode, see the Enabling and Disabling the Output Channels

section.

The VDRx pins provide the gate drive voltage to the internal

power FETs. If the VDR12 voltage falls below 2.9 V (typical),

all channels except LDO1 and LDO2 shut down to prevent

malfunction of the power FETs. As with a PVIN UVLO event,

EN must be toggled to restart channel operation.

Power-On Reset (POR)

If the VBATT voltage falls below its UVLO threshold (VUVLO(BATT)),

all channels, including LDO1 and LDO2, are shut down. This

event forces a power-on reset.

VREG2 is the voltage supply for the internal digital circuit blocks.

If the VREG2 voltage falls below the power-on reset threshold

(VUVLO (POR)) of 2.4 V typical, the ADP5080 shuts down, and all

registers are reset to their default values.

DISCHARGE SWITCH

The ADP5080 integrates discharge switches for Channel 1 to

Channel 7. These switches help to discharge the output capacitors

quickly when a channel is turned off. The discharge switches are

turned on when the EN signal goes low or when a channel is

manually turned off via I2C control, provided that the discharge

function was enabled by setting the DSCGx_ON bit (x is 1 to 7)

in Register 1. The default values for the discharge switches are

factory fuse programmed.

KEEP-ALIVE LDO REGULATORS

The keep-alive LDO linear regulators (LDO1 and LDO2) are kept

alive as long as a valid supply voltage is applied to the VBATT

pin. The LDO regulators are used to power the internal control

block of the ADP5080 so that the device is ready for the enable

(EN) signal. The outputs of LDO1 and LDO2 are also available

via the VREG1 and VREG2 pins for external circuits that are

also kept alive during system standby.

When VBATT initially rises above the UVLO threshold, LDO1

begins operation, followed by LDO2. When all UVLO thresholds

are cleared, the ADP5080 is in standby mode and ready to be

enabled. If an external voltage is used to drive VDDIO, VDDIO

can be on before VBATT; otherwise, LDO2 provides power to

VDDIO via the VREG2 output.

Rev. A | Page 19 of 64

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