ADP5080 datasheet(37/64 Pages) AD

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Data Sheet

ADP5080

External Component Placement and Signal Routing

The majority of the critical switching regulator pins are located

on the outer bumps of the device, making it easier to lay out and

connect to the external components. In general, make traces that

handle large current as wide and short as possible. This consid-

eration applies to the traces for PVINx, SWxA, SWxB, SWx,

PGNDx, and VOUT6.

Make traces that handle switching currents as short as possible.

These critical areas are PVINx, SW6B, VOUT6, and PGNDx.

Reducing the trace length on these nodes helps mitigate noise

coupling. For these connections, avoid using vias because they

add parasitic inductance in the current path. If vias are required

due to routing restrictions, place multiple vias in parallel.

For the buck regulators, the input capacitor has placement

priority. Place the input capacitor as close as possible to the PVINx

and PGNDx pins with wide trace connections. For Channel 6, the

critical component connections are the input capacitor and the

output capacitor. Connect these components as close as possible

to the PVIN6, VOUT6, and PGND6 pins.

For all channels, keep the SWx pin to inductor connection as

short as possible to minimize capacitive coupling. Because the

SWx nodes carry high current, the traces must be wide enough

to handle it.

THERMAL CONSIDERATIONS

The ADP5080 is a high efficiency power converter. However, in

applications with heavy loads at high ambient temperature (TA),

the heat dissipated on the device may exceed the maximum

junction temperature of 125°C. If the junction temperature (TJ)

exceeds 165°C, the ADP5080 enters thermal shutdown (TSD),

and all outputs are disabled. When the junction temperature

falls below approximately 150°C, TSD is cleared. After a TSD

event, the ADP5080 does not restart automatically, but must be

reenabled with the EN pin.

The junction temperature can be calculated using Equation 6.

TJ = TA + TR

(6)

where TR is the rise in junction temperature of the device due

to power dissipation.

The rise in junction temperature is directly proportional to the

power dissipation in the device, as shown in Equation 7.

TR = PDLOSS × θJA

(7)

where:

PDLOSS is the power dissipation in the ADP5080.

θJA is the junction-to-ambient thermal resistance of the package

mounted on a PCB.

The θJA value provided in Table 7 is for a JEDEC standard board.

However, this value is only a benchmark and does not necessarily

correlate to the thermal performance of a real-world PCB.

The thermal performance of the WLCSP package itself is given

by the θJB value (see Table 7). This value is the thermal resistance

from junction to solder ball and varies little with PCB design.

To determine the junction temperature, it is recommended that

the ADP5080 case temperature be measured under worst-case

conditions. The case temperature (TC) is defined as the temper-

ature on the top surface of the device and can be calculated using

Equation 8.

TC = TA + PDLOSS × (θJA − θJC)

(8)

where:

θJC is the junction-to-case thermal resistance of the package,

which is 0.2°C/W.

Because θJC is very low, it can be seen from Equation 9 that the

measured value of TC is a good approximation of TJ.

TJ = TC + TR = TC + PDLOSS × θJC ≈ TC

(9)

The estimated junction temperature or measured case tempera-

ture in worst-case conditions must be less than the maximum

junction temperature of 125°C.

Rev. A | Page 37 of 64

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