ADP5080 datasheet(30/64 Pages) AD

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ADP5080

Data Sheet

Using the Charge Pump as the Channel 7 Input Supply

The charge pump can also be used to generate a high voltage for

the Channel 7 input. This configuration is enabled by adding the

circuit shown in Figure 49 in parallel with the BSTx generating

circuit shown in Figure 48.

Figure 49. Charge Pump Used as a High Voltage Supply for Channel 7

The circuit shown in Figure 49 generates VILDO7 with the

voltage VPVINCP + 2 × VVDR5. In a typical application, this voltage

is equivalent to VVBATT + 10 V to 11 V (PVINCP = VBATT;

VDR5 = VREG1 = 5.5 V or 5 V).

ENABLING AND DISABLING THE OUTPUT

CHANNELS

Each channel (Channel 1 to Channel 7) can be turned on and

off using the sequencer mode or the manual mode. A channel

configured for sequencer mode is automatically turned on and

off by assertion and deassertion of the EN pin, with individually

programmed delay times. A channel configured for manual mode

does not automatically start when EN goes high, but can be turned

on or off via I2C control, as required.

Sequencer Mode

When the MODE_ENx bit (x is 1 to 7) is set in Register 29, the

specified channel turns on and off under the control of the internal

sequencer, which is triggered by the EN pin (see Figure 50).

When the EN pin goes high, each channel controlled by the

sequencer begins a soft start after the delay time specified by the

EN_DLYx bits (see Table 23, Table 25, Table 27, and Table 29).

Similarly, when the EN pin goes low, the channel turns off after

the delay time specified by the DIS_DLYx bits (see Table 31,

Table 33, Table 35, and Table 37).

Note that Figure 50 shows the logical states of each channel; it

does not show soft start and discharge ramps. The disable delay

time for all channels can be increased to four times its configured

value by setting the DIS_DLY_EXTEND bit in Register 35.

When all channels controlled by the sequencer are turned

on, each channel can be manually turned off or on using the

CHx_ON bit (x is 1 to 7) in Register 48. When the CHx_ON

bit is used to turn a channel on or off, the enable state of the

channel changes immediately, regardless of the settings of the

EN_DLYx and DIS_DLYx bits.

When using the sequencer mode, note the following:

•

A channel that is controlled by the sequencer cannot be

turned off manually until after the sequencer turns on all the

channels that it controls and the soft start period has ended.

This ready state can be identified by reading the PWRGx

bits (x is 1 to 7) in Register 24.

•

After the EN pin is asserted, writing to the VIDx bits is

forbidden while the internal sequencer is in operation to

prevent unexpected behavior. The internal sequencer is in

operation from the assertion of the EN pin until the PWRGx

bits in Register 24 go high.

Manual Mode

When the MODE_ENx bit (x is 1 to 7) is cleared in Register 29,

the specified channel turns on and off under I2C control. All

channels that are not configured for sequencer mode can be

manually turned on or off using the CHx_ON bits (x is 1 to 7)

in the PCTRL register (Register 48). Writing 1 to the CHx_ON

bit enables the channel only when the EN pin is logic high.

When the EN pin is taken low, all channels configured for

manual mode turn off immediately, and all the CHx_ON bits

are reset to 0. While the EN pin is low, any data written to or

read from the CHx_ON bits is not valid.

Figure 50. Example Power-Up/Power-Down Sequence Using Sequencer Mode

1µF

VILDO7

VPVINCP + 2VVDR5

BSTCP

C+

PVINCP

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

tDIS_DLY1

OFF

tDIS_DLY2

tDIS_DLY3

tDIS_DLY4

tDIS_DLY5

tDIS_DLY6

tDIS_DLY7

tEN_DLY1

tEN_DLY2

tEN_DLY3

tEN_DLY4

tEN_DLY5

tEN_DLY6

tEN_DLY7

Rev. A | Page 30 of 64

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