ADP5080 datasheet(23/64 Pages) AD

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Data Sheet

ADP5080

Discharge Switch, Channel 1 to Channel 3

Each channel incorporates a discharge switch. For Channel 1

and Channel 2, the discharge switch is located at the FB1 and

FB2 pins, respectively; for Channel 3, the discharge switch is

located at the SW3 pin. The discharge switch can be turned on

when the corresponding channel output is turned off, removing

the residual charge of the external capacitor via a 125 Ω resistor.

The discharge switch can be enabled by setting the appropriate

DSCGx_ON bit in Register 1.

Gate Scaling (Channel 1 Only)

Channel 1 features a gate scaling function, which improves

efficiency in light load conditions. When enabled by setting

the GATE_SCAL1 bit in Register 32, gate scaling halves the size

of the Channel 1 switching FETs, reducing the gate charge-up

current—which is a non-negligible loss element in light load

conditions—while allowing increased RDSON, whose effect is less

significant in these conditions. When gate scaling is enabled,

only SW1A is used for the Channel 1 switch node because it is

assumed that the load current is light.

Dynamic Voltage Scaling (DVS) Function

Channel 1 and Channel 2 incorporate a dynamic voltage scaling

(DVS) function. DVS provides a stair-step transition in output volt-

age when the preset value for the output voltage is reprogrammed

on the fly (see Figure 39).

Figure 39. DVS Operation

The output voltage for Channel 1 is programmed using the VID1

bits in Register 12; the output voltage for Channel 2 is programmed

using the VID2 bits in Register 13. When the DVS function is

enabled, the voltage transition takes place according to the steps

set by the VID1 or VID2 bits (see Table 39 and Table 41). The

transition time from one step to the next is specified by the

interval programmed in Register 17 using the DVSx_INTVAL

bits (where x is 1 or 2). The DVS function is enabled by setting

the EN_DVSx bit in Register 17.

For Channel 2, DVS operation is limited to an output voltage

range of 1.0 V to 1.25 V.

When Channel 1 or Channel 2 is configured for DVS operation,

toggling EN low does not immediately reset the VID code to its

initial state. Instead Channel 1 or Channel 2 returns to its config-

ured output voltage according to the steps set by the VID1 or

VID2 bits (see Table 39 and Table 41, respectively).

Figure 40. Buck Regulator Block Diagram: Channel 1, Channel 2, and Channel 3

OUTPUT VOLTAGE

DVSx_INTVAL

VID (NEW)

VID (PREV)

VID (PREV – 1)

PVINx

SWx

PGNDx

FBx

PGND

PGNDx

4V TO 15V

POWER-GOOD

COMPARATOR

SOFT START

FB1

FB2

SW3

ERROR AMP

PWM

COMPARATOR

PGNDx

CURRENT

SENSE AMP

BSTx

VDRx

VREG1

PGNDx

OVP

UVP

OCP

SEQUENCER

LATCH

PSM LOGIC

ZERO CROSS

COMPARATOR

DISCHARGE

SWITCH

BSTCP

CURRENT

LIMIT

OCP

VREF

ON PERIOD

SLOPE

GENERATION

CLOCK

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

FB3

0.8V

EXTERNAL

VOLTAGE DIVIDER

(CH3 ADJ MODE ONLY)

ADP5080

Rev. A | Page 23 of 64

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