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ADP5080 Datasheet(PDF) 11 Page - Analog Devices |
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ADP5080 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 64 page  Data Sheet ADP5080 Pin No. Mnemonic Description 9C PVIN4 Input Power Supply for Channel 4. 1D SW6A Primary Side Switching Node for Channel 6. 2D SW6A Primary Side Switching Node for Channel 6. 3D VDR6 Low-Side FET Driver Power Supply for Channel 6. Connect this pin to VREG1. 4D FB6 Feedback Node for Channel 6. 5D GND Ground. All GND pins must be connected. 6D SYNC External Clock Input (CMOS Input Port). If this pin is not used, connect it to GND. 7D FB5 Feedback Node for Channel 5. 8D FB4 Feedback Node for Channel 4. 9D SW4 Switching Node for Channel 4. 1E PVIN6 Input Power Supply for Channel 6. 2E PVIN6 Input Power Supply for Channel 6. 3E BST16 High-Side FET Driver Power Supply for Channel 1 and Channel 6. 4E SDA Data Input/Output for I2C Interface. Open-drain I/O port. 5E SCL Clock Input for I2C Interface. For start-up requirements, see the I2C Interface section. 6E GND Ground. All GND pins must be connected. 7E CLKO Clock Output (CMOS Output Port). CLKO replicates the Channel 1 switching clock. This output is not available when the SYNC pin is driven by an external clock. If this pin is not used, leave it open. 8E VDR34 Low-Side FET Driver Power Supply for Channel 3 and Channel 4. Connect this pin to VREG1. 9E PGND4 Power Ground for Channel 4. 1F PVIN1 Input Power Supply for Channel 1. 2F PVIN1 Input Power Supply for Channel 1. 3F FB1 Feedback Node for Channel 1. 4F EN Enable Control Input. 5F VDDIO Supply Voltage for I2C Interface. Typically, this pin is connected externally to VREG2 or to the host I/O voltage. 6F FREQ Frequency Pin for the Internal Oscillator. To select the internal clock source oscillator, connect an external 100 kΩ resistor from the FREQ pin to GND. 7F FB3 Feedback Node for Channel 3. 8F PGND3 Power Ground for Channel 3. 9F PGND3 Power Ground for Channel 3. 1G SW1A Switching Node for Channel 1. 2G SW1B Switching Node for Channel 1. 3G VDR12 Low-Side FET Driver Power Supply for Channel 1 and Channel 2. Connect this pin to VREG1. 4G FB2 Feedback Node for Channel 2. 5G GND Ground. All GND pins must be connected. 6G FAULT Fault Status Output Pin. This open-drain output port goes low when a fault occurs. Leave open if not used. 7G GND Ground. All GND pins must be connected. 8G SW3 Switching Node for Channel 3. 9G SW3 Switching Node for Channel 3. 1H PGND1 Power Ground for Channel 1. 2H PGND1 Power Ground for Channel 1. 3H PGND2 Power Ground for Channel 2. 4H SW2 Switching Node for Channel 2. 5H SW2 Switching Node for Channel 2. 6H PVIN2 Input Power Supply for Channel 2. 7H BST23 High-Side FET Driver Power Supply for Channel 2 and Channel 3. 8H PVIN3 Input Power Supply for Channel 3. 9H PVIN3 Input Power Supply for Channel 3. Rev. A | Page 11 of 64 |
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