ADP5080 datasheet(28/64 Pages) AD

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ADP5080

Data Sheet

SWITCHING CLOCK

The ADP5080 integrates a highly accurate switching clock for the

dc-to-dc converters and the charge pump. As shown in Figure 45,

the internal clock can also be bypassed and the system synchro-

nized to an external clock. When the internal clock source is

used, the switching frequency for each dc-to-dc converter and

the charge pump can be configured.

Figure 45. Switching Clock Distribution

External Synchronization Mode

When an external clock is present at the SYNC pin, all dc-to-dc

converters and the charge pump automatically use it as their

master switching clock; the FREQx bit settings in Register 18 are

ignored. When using external synchronization mode, ensure

that the external clock is already stable before the EN signal is

asserted to avoid unexpected behavior in the converters. When

an external clock is used, the clock must operate within the

specifications listed in Table 1.

Selecting the Internal Clock Frequency

If the SYNC pin is tied high or low, the device uses the internal

clock. The internal oscillator generates a master clock at either

2.0 MHz or 1.5 MHz, as specified by the SEL_FSW bit in

The master clock is divided down by half so that each dc-to-dc

converter can select 1× or 1/2× the master clock frequency. The

frequency of each channel is set using the FREQx bit (where x is

1 to 6) in Register 18. For example, if the master clock is set to

1.5 MHz, Channel 1 through Channel 6 can be configured to

operate at 750 kHz or 1.5 MHz, but not at 1 MHz or 2 MHz.

For the charge pump, the FREQ_CP bits set the switching

frequency (see the Charge Pump Switching Frequency section).

Selecting the External Resistor

An external 100 kΩ resistor from the FREQ pin to GND is

required for the internal clock source oscillator. To obtain an

accurate clock frequency, select a high precision resistor with

a low temperature coefficient. A 1 nF bypass capacitor is also

recommended at the FREQ pin.

Phase Shifting

Each dc-to-dc converter can be configured to use the inverted

phase of the master clock by setting the PHASEx bit (where x is

1 to 6) in Register 20. Setting channels out of phase with each

other helps reduce rms current stress on the input capacitors and

spreads switching energy over two cycles. Phase shifting reduces

possible interference in a system due to propagated switching

noise on the input rail.

When any channel is operated at 1/2 × fSW, the higher frequency

channel must be set out of phase to have any effect on the

apparent phase of the lower frequency channel (see Figure 46).

Figure 46. Switching Phase Relationships

Any channel at 1 × fSW has the expected, set phase relationship to

the master clock. However, when a channel operates at 1/2 × fSW,

it always appears to be in phase with the master clock and with

any in-phase channel at 1 × fSW. This relationship is illustrated

by the lines labeled 1 and 2 in Figure 46; regardless of the phase

setting, Line 1 or Line 2 is always aligned to the rising edge.

To set a channel operating at 1/2 × fSW out of phase, the highest

frequency channel must be set out of phase. Referring to the lines

labeled 3 in Figure 46, the channel operating at 1/2 × fSW is now

out of phase with the channel operating at 1 × fSW, regardless of

the phase setting.

CLKO Pin

The clock output (CLKO) pin can output the internal switching

clock used for Channel 1. The output is enabled by setting the

EN_CLKO bit in Register 19 to 1. The CLKO output stays low

when external clocking is used or when the EN_CLKO bit is set

to 0.

CH1

CH2

FREQx

ROSC

100kΩ

FREQ

CLOCK

SOURCE

2.0MHz (0)

1.5MHz (1)

SEL_FSW

SYNC

DETECTOR

CHARGE

PUMP

1/8

FREQ_CP[0]

PHASEx

EN_CLKO

CLKO

SYNC

DETECTOR

1/2

FREQ_CP[1]

CH3

CH4

CH5

CH6

1/2

IN PHASE

OUT OF PHASE

IN PHASE

OUT OF PHASE

MASTER CLOCK

2MHz

1MHz

Rev. A | Page 28 of 64

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