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PEB2256HT Datasheet(PDF) 316 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 316 Page - Infineon Technologies AG |
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316 / 490 page  FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 316 2002-08-27 Interrupt Status Register 3 (Read) All bits are reset when ISR3 is read. If bit GCR.VIS is set, interrupt statuses in ISR3 are flagged although they are masked by register IMR3. However, these masked interrupt statuses neither generate a signal on INT, nor are visible in register GIS. ES Errored Second This bit is set if at least one enabled interrupt source by ESM is set during the time interval of one second. Interrupt sources of ESM register: LFA = Loss of frame alignment detected (FRS0.LFA) FER = Framing error received CER = CRC error received AIS = Alarm indication signal (FRS0.AIS) LOS = Loss-of-signal (FRS0.LOS) CVE = Code violation detected SLIP = Receive Slip positive/negative detected EBE = E-Bit error detected (RSP.RS13/15) SEC Second Timer The internal one-second timer has expired. The timer is derived from clock RCLK or external pin SEC/FSC. LMFA16 Loss of Multiframe Alignment TS 16 Multiframe alignment of time slot 16 has been lost if two consecutive multiframe pattern are not detected or if in 16 consecutive time slot 16 all bits are reset. If register GCR.SCI is high this interrupt status bit is set with every change of state of FRS1.TS16LFA. AIS16 Alarm Indication Signal TS 16 Status Change The alarm indication signal AIS in time slot 16 for the 64 kbit/s channel associated signaling is detected or cleared. A change in bit FRS1.TS16AIS sets this interrupt. (This bit is set if the incoming TS 16 signal contains less than 4 zeros in each of two consecutive TS16- multiframe periods.) 70 ISR3 ES SEC LMFA16 AIS16 RA16 RSN RSP (6B) |
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