PEB2256HT datasheet(313/490 Pages) INFINEON

313 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

313

2002-08-27

RDO

Receive Data Overflow - HDLC Channel 1

This interrupt status indicates that the CPU did not respond fast

enough to an RPF or RME interrupt and that data in RFIFO has been

lost. Even when this interrupt status is generated, the frame continues

to be received when space in the RFIFO is available again.

Note: Whereas the bit RSIS.RDO in the frame status byte indicates

whether an overflow occurred when receiving the frame

currently accessed in the RFIFO, the ISR1.RDO interrupt

status is generated as soon as an overflow occurs and does

not necessarily pertain to the frame currently accessed by the

processor.

ALLS

All Sent - HDLC Channel 1

This bit is set if the last bit of the current frame has been sent

completely and XFIFO is empty. This bit is valid in HDLC mode only.

XDU

Transmit Data Underrun - HDLC Channel 1

Transmitted frame was terminated with an abort sequence because

no data was available for transmission in XFIFO and no XME was

issued.

Note: Transmitter and XFIFO are reset and deactivated if this

condition occurs. They are reactivated not before this interrupt

status register has been read. Thus, XDU should not be

masked by register IMR1.

XMB

Transmit Multiframe Begin

This bit is set every 2 ms with the beginning of a transmitted

multiframe related to the internal transmit line interface timing.

Just before setting this bit registers XS(16:1) are copied in the

transmit shift registers. The registers XS(16:1) are empty and has to

be updated otherwise the contents is retransmitted.

SUEX

Signaling Unit Error Threshold Exceeded - HDLC Channel 1

Masks the indication by interrupt that the selected error threshold for

SS7 signaling units has been exceeded.

0 =

Signaling unit error count below selected threshold

1 =

Signaling unit error count exceeded selected threshold

Note: SUEX is only valid, if SS7 mode is selected.

If SUEX is caused by an aborted/invalid frame, the interrupt will be

issued regularly until a valid frame is received (e.g. a FISU).

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