PEB2256HT datasheet(310/490 Pages) INFINEON

310 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

310

2002-08-27

Receive Byte Count Low - HDLC Channel 1 (Read)

Together with RBCH, bits RBC(11:8), indicates the length of a

received frame (1 to 4095 bytes). Bits RBC(4:0) indicate the number

of valid bytes currently in RFIFO. These registers must be read by the

CPU following a RME interrupt.

Received Byte Count High - HDLC Channel 1 (Read)

Value after reset: 000

xxxxx

Counter Overflow - HDLC Channel 1

More than 4095 bytes received.

RBC(11:8)

Receive Byte Count - HDLC Channel 1 (most significant bits)

Together with RBCL, bits RBC(7:0) indicates the length of the

received frame.

Interrupt Status Register 0 (Read)

Value after reset: 00

All bits are reset when ISR0 is read.

If bit GCR.VIS is set, interrupt statuses in ISR0 are flagged although they are masked by

INT, nor are visible in register GIS.

RME

Receive Message End - HDLC Channel 1

One complete message of length less than 32 bytes, or the last part

of a frame at least 32 bytes long is stored in the receive FIFO,

including the status byte.

RBCL

RBC7

RBC0

(66)

RBCH

RBC11

RBC10

RBC9

RBC8

(67)

ISR0

RME

RFS

T8MS

RMB

CASC

CRC4

SA6SC

RPF

(68)

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