PEB2256HT datasheet(307/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

307

2002-08-27

Signaling Status Register (Read)

XDOV

Transmit Data Overflow - HDLC Channel 1

More than 32 bytes have been written to the XFIFO.

This bit is reset

– by a transmitter reset command XRES

– when all bytes in the accessible half of the XFIFO have been moved

in the inaccessible half.

XFW

Transmit FIFO Write Enable - HDLC Channel 1

Data can be written to the XFIFO.

XREP

Transmission Repeat - HDLC Channel 1

Status indication of CMDR.XREP.

RLI

Receive Line Inactive - HDLC Channel 1

Neither flags as interframe time fill nor frames are received through

the signaling time slot.

CEC

Command Executing - HDLC Channel 1

0 =

No command is currently executed, the CMDR register can be

written to.

1 =

A command (written previously to CMDR) is currently executed,

no further command can be temporarily written in CMDR

Note: CEC is active for about 2.5 periods of the current system data

rate.

SFS

Status Freeze Signaling

0 =

Freeze signaling status inactive.

1 =

Freeze signaling status active

SIS

XDOV

XFW

XREP

RLI

CEC

SFS

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PEB2256HT Datasheet(PDF) 307 Page - Infineon Technologies AG

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