PEB2256HT datasheet(303/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

303

2002-08-27

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then reset automatically. The latched error

counter state should be read within the next second.

CRC Error Counter 3 (Read)

CE(15:0)

CRC Error Counter (detected at T Reference Point in S

a6 -Bit)

GCR.ECMC = 0: If doubleframe format is selected, CEC3H/L has no

function. If CRC-multiframe mode is enabled, CEC3H/L works as S

a6-

bit error indication counter (16 bits) which counts the S

a6-bit

sequence 0010 and 0011in every received CRC submultiframe.

Incrementing the counter is only possible in the multiframe

synchronous state FRS0.LMFA = 0.

a6-bit sequence: SA61, SA62, SA63, SA64 = 0010 or 0011 where

SA61 is received in frame 1 or 9 in every multiframe. The error

counter does not roll over.

During alarm simulation, the counter is incremented once per

submultiframe up to its saturation.

CE(7:2)

Multiframe Counter

GCR.ECMC = 1: This 6 bit counter increments with each multiframe

period in the asynchronous state FRS0.LFA/LMFA = 1.

During alarm simulation, the counter is incremented once per

multiframe up to its saturation.

CE(1:0)

Change of Frame Alignment Counter

GCR.ECMC = 1: This 2 bit counter increments with each detected

change of frame/multiframe alignment. The error counter does not roll

over.

During alarm simulation, the counter is incremented once per

multiframe up to its saturation.

Clearing and updating the counter is done according to bit

FMR1.ECM.

CEC3L

CE7

CE0

(5A)

CEC3H

CE15

CE8

(5B)

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