PEB2256HT datasheet(302/490 Pages) INFINEON

302 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

302

2002-08-27

CRC Error Counter 2 (Read)

CC(15:0)

CRC Error Counter (reported from TE through S

a6 -Bit)

Depending on bit LCR1.EPRM the error counter increment is

selected:

LCR1.EPRM = 0:

If doubleframe format is selected, CEC2H/L has no function. If CRC-

multiframe mode is enabled, CEC2H/L works as S

a6-bit

error

indication counter (16 bits) which counts the S

a6-bit sequence 0001

and 0011in every received CRC submultiframe.

Incrementing the counter is only possible in the multiframe

synchronous state FRS0.LMFA = 0.

a6-bit sequence: SA61, SA62, SA63, SA64 = 0001 or 0011 where

SA61 is received in frame 1 or 9 in every multiframe.

During alarm simulation, the counter is incremented once per

submultiframe up to its saturation.

Pseudo-Random Binary Sequence Error Counter

LCR1.EPRM = 1:

This 16-bit counter is incremented with every received PRBS bit error

in the PRBS synchronous state RSP.LLBAD = 1. The error counter

does not roll over.

During alarm simulation, the counter is incremented continuously with

every second received bit.

Clearing and updating the counter is done according to bit

FMR1.ECM.

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the error counter bit DEC.DCEC2

has to be set. With the rising edge of this bit updating of the buffer is

stopped and the error counter is reset. Bit DEC.DCEC2 is reset

automatically with reading the error counter high byte.

CEC2L

CC7

CC0

(58)

CEC2H

CC15

CC8

(59)

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