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PEB2256HT Datasheet(PDF) 305 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 305 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
E1 Registers
Data Sheet
305
2002-08-27
Receive S
a6-Bit Status (Read)
Four consecutive received S
a6-bits
are checked on the by
ETS300233 defined S
a6-bit combinations. The FALC56 detects the
following “fixed” S
a6-bit combinations:
SA61, SA62, SA63, SA64 = 1000, 1010, 1100, 1110, 1111. All other
possible 4 bit combinations are grouped to status “X”.
A valid S
a6-bit combination must occur three times in a row. The
corresponding status bit in this register is set. Even if the detected
status is active for a short time the status bit remains active until this
register is read. Reading the register resets all pending status
information.
With any change of state of the S
a6-bit combinations an interrupt
status ISR0.SA6SC is generated.
During the basic frame asynchronous state updating of this register
and interrupt status ISR0.SA6SC is disabled. In multiframe format the
detection of the S
a6-bit combinations can be done either synchronous
or
asynchronous
to
the
submultiframe
(FMR3.SA6SY).
In
synchronous detection mode updating of register RSA6S is done in
the
multiframe
synchronous
state
(FRS0.LMFA = 0).
In
asynchronous detection mode updating is independent to the
multiframe synchronous state.
S_X
Receive S
a6-Bit Status_X
If none of the fixed S
a6-bit combinations are detected this bit is set.
S_F
Receive S
a6-Bit Status: "1111"
Receive S
a6-bit status “1111” is detected for three times in a row in
the S
a6-bit positions.
S_E
Receive S
a6-Bit Status: "1110"
Receive S
a6-bit status “1110” is detected for three times in a row in
the S
a6-bit positions.
S_C
Receive S
a6-Bit Status: "1100"
Receive S
a6-bit status “1100” is detected for three times in a row in
the S
a6bit positions.
70
RSA6S
S_X
S_F
S_E
S_C
S_A
S_8
(61)



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