PEB2256HT datasheet(304/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

304

2002-08-27

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the error counter bit DEC.DCEC3

has to be set. With the rising edge of this bit updating of the buffer is

stopped and the error counter is reset. Bit DEC.DCEC3 is reset

automatically with reading the error counter high byte.

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then automatically reset. The latched error

counter state should be read within the next second.

Receive S

a4-Bit Register (Read)

RS4(7:0)

Receive S

a4-Bit Data (Y-Bits)

RS5(7:0)

Receive S

a5-Bit Data

RS6(7:0)

Receive S

a6-Bit Data

RS7(7:0)

Receive S

a7-Bit Data

RS8(7:0)

Receive S

a8-Bit Data

This register contains the information of the eight S

ax bits (x = 4 to 8)

of the previously received CRC multiframe. These registers are

updated with every multiframe begin interrupt ISR0.RMB.

RS40 is received in bit-slot 4 of every service word in frame 1, RS47

in frame 15

RS50 is received in bit-slot 5, time slot 0, frame 1, RS57 in frame 15

RS60 is received in bit-slot 6, time slot 0, frame 1, RS67 in frame 15

RS70 is received in bit-slot 7, time slot 0, frame 1, RS77 in frame 15

RS80 is received in bit-slot 8, time slot 0, frame 1, RS87 in frame 15

Valid if CRC multiframe format is enabled by setting bits

FMR2.RFS1 = 1 or FMR2.RFS(1:0) = 01 (doubleframe format).

RSA4

RS47

RS40

(5C)

RSA5

RS57

RS50

(5D)

RSA6

RS67

RS60

(5E)

RSA7

RS77

RS70

(5F)

RSA8

RS87

RS80

(60)

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