PEB2256HT datasheet(300/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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300 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

300

2002-08-27

CRC Error Counter 1 (Read)

CR(15:0)

CRC Errors

No function if doubleframe format is selected.

In CRC-multiframe mode, the 16-bit counter is incremented when a

CRC-submultiframe has been received with a CRC error. CRC errors

are not counted during asynchronous state. The error counter does

not roll over.

During alarm simulation, the counter is incremented once per

submultiframe up to its saturation.

Clearing and updating the counter is done according to bit

FMR1.ECM.

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the error counter bit DEC.DCEC1

has to be set. With the rising edge of this bit updating the buffer is

stopped and the error counter is reset. Bit DEC.DCEC1 is reset

automatically with reading the error counter high byte.

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then automatically reset. The latched error

counter state should be read within the next second.

CEC1L

CR7

CR0

(54)

CEC1H

CR15

CR8

(55)

PEB2256HT Datasheet(PDF) 300 Page - Infineon Technologies AG