PEB2256HT datasheet(298/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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298 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

298

2002-08-27

Framing Error Counter (Read)

FE(15:0)

Framing Errors

This 16-bit counter is incremented when a FAS word has been

received with an error.

Framing errors are counted during basic frame synchronous state

only (but even if multiframe synchronous state is not reached yet).

During alarm simulation, the counter is incremented every 250

µs up

to its saturation. The error counter does not roll over.

Clearing and updating the counter is done according to bit

FMR1.ECM.

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the error counter bit DEC.DFEC has

to be set. With the rising edge of this bit updating the buffer is stopped

and the error counter is reset. Bit DEC.DFEC is reset automatically

with reading the error counter high byte.

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then automatically reset. The latched error

counter state should be read within the next second.

FECL

FE7

FE0

(50)

FECH

FE15

FE8

(51)

PEB2256HT Datasheet(PDF) 298 Page - Infineon Technologies AG