PEB2256HT datasheet(295/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

295

2002-08-27

XLS

Transmit Line Short

Significant only if the ternary line interface is selected by

LIM1.DRS = 0.

0 =

Normal operation. No short is detected.

1 =

The XL1 and XL2 are shortened for at least 3 pulses. As a

reaction of the short the pins XL1 and XL2 are automatically

forced into a high-impedance state if bit XPM2.DAXLT is reset.

After 128 consecutive pulse periods the outputs XL1/2 are

activated again and the internal transmit current limiter is

checked. If a short between XL1/2 is still further active the

outputs XL1/2 are in high-impedance state again. When the

short disappears pins XL1/2 are activated automatically and

this bit is reset. With any change of this bit an interrupt

ISR1.XLSC is generated. In case of XPM2.XLT is set this bit is

frozen.

XLO

Transmit Line Open

0 =

Normal operation

1 =

This bit is set if at least 32 consecutive zeros were sent on pins

XL1/XL2 or XDOP/XDON. This bit is reset with the first

transmitted pulse. With the rising edge of this bit an interrupt

ISR1.XLSC is set. In case of XPM2.XLT is set this bit is frozen.

Receive Service Word Pulseframe (Read)

RSI

Receive Spare Bit for International Use

First bit of the received service word. It is fixed to one if CRC-

multiframe mode is enabled.

RRA

Receive Remote Alarm

Equivalent to bit FRS0.RRA.

RY(4:0)

Receive Spare Bits for National Use (Y-Bits, S

n-Bits, Sa-Bits)

RSW

RSI

RRA

RY0

RY1

RY2

RY3

RY4

(4E)

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