PEB2256HT datasheet(296/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

296

2002-08-27

Receive Spare Bits/Additional Status (Read)

SI(2:1)

Submultiframe Error Indication 1, 2

Not valid if doubleframe format is enabled. In this case, both bits are

set.

When using CRC-multiframe format these bits are set to

0 =

If multiframe alignment has been lost, or if the last multiframe

has been received with CRC error(s).

SI1 flags a CRC error in last submultiframe 1, SI2 flags a CRC

error in last submultiframe 2.

1 =

If at multiframe synchronous state last assigned submultiframe

has been received without a CRC error.

Both flags are updated with the beginning of every received CRC

multiframe.

If automatic transmission of submultiframe status is enabled by

setting

bit

XSP.AXS,

above

status

information

inserted

automatically in S

i-bit position of every outgoing CRC multiframe

(under the condition that time slot 0 transparent modes are both

disabled):

SI1

→ S

i -bit of frame 13, SI2 → Si -bit of frame 15.

LLBDD

Line Loop-Back Deactivation Signal Detected

This bit is set in case of the LLB deactivate signal is detected and then

received over a period of more than 25 ms with a bit error rate less

than 10

-2. The bit remains set as long as the bit error rate does not

exceed 10

-2.

If framing is aligned, the time slot 0 is not taken into account for the

error rate calculation.

Any change of this bit causes an LLBSC interrupt.

LLBAD

Line Loop-Back Activation Signal Detected

Depending on bit LCR1.EPRM the source of this status bit changed.

LCR1.EPRM = 0: This bit is set in case of the LLB activate signal is

detected and then received over a period of more than 25 ms with a

bit error rate less than 10

-2. The bit remains set as long as the bit error

rate does not exceed 10

-2.

RSP

SI1

SI2

LLBDD

LLBAD

RSIF

RS13

RS15

(4F)

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