PEB2256HT datasheet(291/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

291

2002-08-27

Framer Receive Status Register 0 (Read)

LOS

Loss-of-Signal

Detection:

This bit is set when the incoming signal has “no transitions” (analog

interface) or logical zeros (digital interface) in a time interval of T

consecutive pulses, where T is programmable by register PCD.

Total account of consecutive pulses: 16 < T < 4096.

Analog interface: The receive signal level where “no transition” is

declared is defined by the programmed value of LIM1.RIL(2:0).

Recovery:

Analog interface: The bit is reset in short-haul mode when the

incoming signal has transitions with signal levels greater than the

programmed receive input level (LIM1.RIL(2:0)) for at least M pulse

periods defined by register PCR in the PCD time interval. In long-haul

mode additionally bit RES.6 must be set for at least 250µsec.

Digital interface: The bit is reset when the incoming data stream

contains at least M ones defined by register PCR in the PCD time

interval.

With the rising edge of this bit an interrupt status bit (ISR2.LOS) is set.

The bit is also set during alarm simulation and reset, if FMR0.SIM is

cleared and no alarm condition exists.

AIS

Alarm Indication Signal

The function of this bit is determined by FMR0.ALM.

FMR0.ALM = 0: This bit is set when two or less zeros in the received

bit stream are detected in a time interval of 250

µs and the FALC56 is

in asynchronous state (FRS0.LFA = 1). The bit is reset when no

alarm condition is detected (according to ETSI standard).

FMR0.ALM = 1: This bit is set when the incoming signal has two or

less Zeros in each of two consecutive double frame period (512 bits).

This bit is cleared when each of two consecutive doubleframe periods

contain three or more zeros or when the frame alignment signal FAS

has been found. (ITU-T G.775)

The bit is also set during alarm simulation and reset if FMR0.SIM is

cleared and no alarm condition exists.

With the rising edge of this bit an interrupt status bit (ISR2.AIS) is set.

FRS0

LOS

AIS

LFA

RRA

NMF

LMFA

(4C)

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