PEB2256HT datasheet(289/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

289

2002-08-27

9.4

Detailed Description of E1 Status Registers

Receive FIFO - HDLC Channel 1 (Read)

Reading data from RFIFO of HDLC channel 1 can be done in an 8-bit (byte) or 16-bit

(word) access depending on the selected bus interface mode. The LSB is received first

from the serial interface.

The size of the accessible part of RFIFO is determined by programming the bits

CCR1.RFT(1:0) (RFIFO threshold level). It can be reduced from 32 bytes (reset value)

down to 2 bytes (four values: 32, 16, 4, 2 bytes).

Data Transfer

Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF

or an RME interrupt.

RPF Interrupt: A fixed number of bytes/words to be read (32, 16, 4, 2 bytes). The

message is not yet complete.

RME Interrupt: The message is completely received. The number of valid bytes is

determined by reading the RBCL, RBCH registers.

RFIFO is released by issuing the RMC (Receive Message Complete) command.

Receive Buffer Delay (Read)

RBD(5:0)

Receive Elastic Buffer Delay

These bits informs the user about the current delay (in time slots)

through the receive elastic buffer. The delay is updated every 512 or

256 bits (SIC1.RBS(1:0)). Before reading this register the user has to

set bit DEC.DRBD in order to halt the current value of this register.

After reading RBD updating of this register is enabled. Not valid if the

receive buffer is bypassed.

000000 = Delay < 1 time slot

...

111111 = Delay > 63 time slots

RFIFO

RF7

RF0

(00)

RFIFO

RF15

RF8

(01)

RBD

RBD5

RBD4

RBD3

RBD2

RBD1

RBD0

(49)

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