PEB2256HT datasheet(301/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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301 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

301

2002-08-27

E-Bit Error Counter (Read)

EB(15:0)

E-Bit Errors

If doubleframe format is selected, FEBEH/L has no function. If CRC-

multiframe mode is enabled, FEBEH/L works as submultiframe error

indication counter (16 bits) which counts zeros in S

i-bit position of

frame 13 and 15 of every received CRC multiframe. The error counter

does not roll over.

During alarm simulation, the counter is incremented once per

submultiframe up to its saturation.

Clearing and updating the counter is done according to bit

FMR1.ECM.

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the error counter bit DEC.DEBC

has to be set. With the rising edge of this bit updating the buffer is

stopped and the error counter is reset. Bit DEC.DEBC is reset

automatically with reading the error counter high byte.

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then automatically reset. The latched error

counter state should be read within the next second.

EBCL

EB7

EB0

(56)

EBCH

EB15

EB8

(57)

PEB2256HT Datasheet(PDF) 301 Page - Infineon Technologies AG