PEB2256HT datasheet(311/490 Pages) INFINEON

311 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

311

2002-08-27

The complete message length can be determined reading the RBCH,

RBCL registers, the number of bytes currently stored in RFIFO is

given by RBC(4:0). Additional information is available in the RSIS

RFS

Receive Frame Start - HDLC Channel 1

This is an early receiver interrupt activated after the start of a valid

frame has been detected, i.e. after an address match (in operation

modes providing address recognition), or after the opening flag

(transparent mode 0) is detected, delayed by two bytes. After an RFS

interrupt, the contents of

• RAL1

• RSIS bits 3 to 1

are valid and can be read by the CPU.

T8MS

Receive Time Out 8 ms

Only active if multiframing is enabled.

The

framer

has

found

the

double

framing

(basic

framing)

FRS0.LFA = 0 and is searching for the multiframing. This interrupt is

set to indicate that no multiframing was found within a time window of

8 ms. In multiframe synchronous state this interrupt is not generated.

Refer also to floating multiframe alignment window.

RMB

Receive Multiframe Begin

This bit is set with the beginning of a received CRC multiframe related

to the internal receive line timing.

In CRC multiframe format FMR2.RFS1 = 1 or in doubleframe format

FMR2.RFS(1:0) = 01

this

interrupt

occurs

every

ms.

FMR2.RFS(1:0) = 00 this interrupt is generated every doubleframe

(512 bits).

CASC

Received CAS Information Changed

This bit is set with the updating of a received CAS multiframe

information in the registers RS(16:1). If the last received CAS

information is different to the previous received one, this interrupt is

generated after update has been completed. This interrupt only

occurs only in TS0 and TS16 synchronous state. The registers

RS(16:1) should be read within the next 2 ms otherwise the contents

is lost.

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