PEB2256HT datasheet(314/490 Pages) INFINEON

314 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

314

2002-08-27

XLSC

Transmit Line Status Change

XLSC is set with the rising edge of the bit FRS1.XLO or with any

change of bit FRS1.XLS.

The actual status of the transmit line monitor can be read from the

FRS1.XLS and FRS1.XLO.

XPR

Transmit Pool Ready - HDLC Channel 1

A data block of up to 32 bytes can be written to the transmit FIFO.

XPR enables the fastest access to XFIFO. It has to be used for

transmission of long frames, back-to-back frames or frames with

shared flags.

Interrupt Status Register 2 (Read)

All bits are reset when ISR2 is read.

If bit GCR.VIS is set, interrupt statuses in ISR2 are flagged although they are masked by

INT, nor are visible in register GIS.

FAR

Frame Alignment Recovery

The framer has reached doubleframe synchronization. Set when bit

FRS0.LFA is reset. It is set also after alarm simulation is finished and

the receiver is still synchronous.

LFA

Loss of Frame Alignment

The framer has lost synchronization and bit FRS0.LFA is set. It is set

during alarm simulation.

MFAR

Multiframe Alignment Recovery

Set when the framer has found two CRC-multiframes at an interval of

× 2 ms (n = 1, 2, 3, and so forth) without a framing error. At the

same time bit FRS0.LMFA is reset.

It is set also after alarm simulation is finished and the receiver is still

synchronous. Only active if CRC-multiframe format is selected.

ISR2

FAR

LFA

MFAR

T400MS

AIS

LOS

RAR

(6A)

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