PEB2256HT datasheet(320/490 Pages) INFINEON

320 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

320

2002-08-27

RME3

Receive Message End - HDLC Channel 3

One complete message of length less than 32 bytes, or the last part

of a frame at least 32 bytes long is stored in the receive FIFO3,

including the status byte.

The complete message length can be determined reading register

RBC3, the number of bytes currently stored in RFIFO3 is given by

RBC3(6:0). Additional information is available in register RSIS3.

RFS3

Receive Frame Start - HDLC Channel 3

This is an early receiver interrupt activated after the start of a valid

frame has been detected, i.e. after an address match (in operation

modes providing address recognition), or after the opening flag

(transparent mode 0) is detected, delayed by two bytes. After an

RFS2 interrupt, the contents of

• RAL1

• RSIS3 bits 3 to 1

are valid and can be read by the CPU.

RDO3

Receive Data Overflow - HDLC Channel 3

This interrupt status indicates that the CPU did not respond fast

enough to an RPF3 or RME3 interrupt and that data in RFIFO3 has

been lost. Even when this interrupt status is generated, the frame

continues to be received when space in the RFIFO3 is available

again.

Note: Whereas the bit RSIS3.RDO3 in the frame status byte

indicates whether an overflow occurred when receiving the

frame currently accessed in the RFIFO3, the ISR5.RDO3

interrupt status is generated as soon as an overflow occurs

and does not necessarily pertain to the frame currently

accessed by the processor.

ALLS3

All Sent - HDLC Channel 3

This bit is set if the last bit of the current frame has been sent

completely and XFIFO3 is empty. This bit is valid in HDLC mode only.

PEB2256HT Datasheet(PDF) 320 Page - Infineon Technologies AG