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PEB2256HT Datasheet(PDF) 324 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 324 Page - Infineon Technologies AG |
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324 / 490 page ![]() FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 324 2002-08-27 XFW2 Transmit FIFO Write Enable - HDLC Channel 2 Data can be written to the XFIFO2. XREP2 Transmission Repeat - HDLC Channel 2 Status indication of CMDR2.XREP2. RLI2 Receive Line Inactive - HDLC Channel 2 Neither flags as interframe time fill nor frames are received via the signaling time slot. CEC2 Command Executing - HDLC Channel 2 0 = No command is currently executed, the CMDR3 register can be written to. 1 = A command (written previously to CMDR3) is currently executed, no further command can be temporarily written in CMDR3 register. Note: CEC2 will be active at most 2.5 periods of the current system data rate. |
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