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PEB2256HT Datasheet(PDF) 328 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 328 Page - Infineon Technologies AG |
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328 / 490 page ![]() FALC56 V1.2 PEB 2256 E1 Registers Data Sheet 328 2002-08-27 Note: Shorter frames are not reported. RDO3 Receive Data Overflow - HDLC Channel 3 A data overflow has occurred during reception of the frame. Additionally, an interrupt can be generated (refer to ISR5.RDO3/IMR5.RDO3). CRC163 CRC16 Compare/Check - HDLC Channel 3 0 = CRC check failed; received frame contains errors. 1 = CRC check o.k.; received frame is error-free. RAB3 Receive Message Aborted - HDLC Channel 3 This bit is set, if more than 5 contiguous 1-bits are detected. HA13, HA03 High Byte Address Compare - HDLC Channel 3 Significant only if 2-byte address mode is selected. In operating modes which provide high byte address recognition, the FALC ® compares the high byte of a 2-byte address with the contents of two individually programmable registers (RAH1, RAH2) and the fixed values FE H and FCH (broadcast address). Depending on the result of this comparison, the following bit combinations are possible: 00 = RAH2 has been recognized 01 = Broadcast address has been recognized 10 = RAH1 has been recognized C/R=0 (bit 1) 11 = RAH1 has been recognized C/R=1 (bit 1) Note: If RAH1, RAH2 contain identical values, a match is indicated by "10" or "11". LA3 Low Byte Address Compare - HDLC Channel 3 Significant in HDLC modes only. The low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (RAL1, RAL2). 0 = RAL2 has been recognized 1 = RAL1 has been recognized |
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