PEB2256HT datasheet(325/490 Pages) INFINEON

325 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

325

2002-08-27

Receive Signaling Status Register 2 (Read)

Value after reset: 00

RSIS2 relates to the last received HDLC channel 2 frame; it is copied into RFIFO2 when

end-of-frame is recognized (last byte of each stored frame).

VFR2

Valid Frame - HDLC Channel 2

Determines whether a valid frame has been received.

Valid

Invalid

An invalid frame is either

– a frame which is not an integer number of 8 bits (n

×8 bits) in length

(e.g. 25 bits), or

– a frame which is too short taking into account the operation mode

selected via MODE2 (MDS2(2:0)) and the selection of receive CRC

ON/OFF (CCR3.RCRC2) as follows:

• MDS2(2:0)=011 (16 bit Address),

RCRC2=0: 4 bytes; RCRC2=1: 3 or 4 bytes

• MDS2(2:0)=010 (8 bit Address),

RCRC2=0: 3 bytes; RCRC2=1: 2 or 3 bytes

Note: Shorter frames are not reported.

RDO2

Receive Data Overflow - HDLC Channel 2

A data overflow has occurred during reception of the frame.

Additionally, an interrupt can be generated

(refer to ISR4.RDO2/IMR4.RDO2).

CRC162

CRC16 Compare/Check - HDLC Channel 2

= CRC check failed; received frame contains errors.

= CRC check o.k.; received frame is error-free.

RAB2

Receive Message Aborted - HDLC Channel 2

This bit is set, if more than 5 contiguous 1-bits are detected.

RSIS2

VFR2

RDO2

CRC162

RAB2

HA12

HA02

LA2

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PEB2256HT Datasheet(PDF) 325 Page - Infineon Technologies AG

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