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PEB2256HT Datasheet(PDF) 321 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 321 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
E1 Registers
Data Sheet
321
2002-08-27
XDU3
Transmit Data Underrun - HDLC Channel 3
Transmitted frame was terminated with an abort sequence because
no data was available for transmission in XFIFO3 and no XME3 was
issued.
Note: Transmitter and XFIFO3 are reset and deactivated if this
condition occurs. They are reactivated not before this interrupt
status register has been read. Thus, XDU3 should not be
masked via register IMR5.
RPF3
Receive Pool Full - HDLC Channel 3
32 bytes of a frame have arrived in the receive FIFO3. The frame is
not yet completely received.
Global Interrupt Status Register (Read)
Value after reset: 00
H
This status register points to pending interrupts sourced by ISR(5:0).
70
GIS
ISR5
ISR4
ISR3
ISR2
ISR1
ISR0
(6E)



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