PEB2256HT datasheet(327/490 Pages) INFINEON

327 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

327

2002-08-27

XREP3

Transmission Repeat - HDLC Channel 3

Status indication of CMDR3.XREP3.

RLI3

Receive Line Inactive - HDLC Channel 3

Neither flags as interframe time fill nor frames are received via the

signaling time slot.

CEC3

Command Executing - HDLC Channel 3

= No command is currently executed, the CMDR4 register can be

written to.

= A command (written previously to CMDR4) is currently

executed, no further command can be temporarily written in

CMDR4 register.

Note: CEC3 will be active up to 2.5 periods of the current system data

rate.

Receive Signaling Status Register 3 (Read)

Value after reset: 00

RSIS3 relates to the last received HDLC channel 3 frame; it is copied into RFIFO3 when

end-of-frame is recognized (last byte of each stored frame).

VFR3

Valid Frame - HDLC Channel 3

Determines whether a valid frame has been received.

Valid

Invalid

An invalid frame is either

– a frame which is not an integer number of 8 bits (n

×8 bits) in length

(e.g. 25 bits), or

– a frame which is too short taking into account the operation mode

selected via MODE3 (MDS3(2:0)) and the selection of receive CRC

ON/OFF (CCR4.RCRC3) as follows:

• MDS3(2:0)=011 (16 bit Address),

RCRC3=0: 4 bytes; RCRC3=1: 3 or 4 bytes

• MDS3(2:0)=010 (8 bit Address),

RCRC3=0: 3 bytes; RCRC3=1: 2 or 3 bytes

RSIS3

VFR3

RDO3

CRC163

RAB3

HA13

HA03

LA3

(9B)

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