PEB2256HT datasheet(326/490 Pages) INFINEON

326 / 490 page

FALC56 V1.2

PEB 2256

E1 Registers

Data Sheet

326

2002-08-27

HA12, HA02

High Byte Address Compare - HDLC Channel 2

Significant only if 2-byte address mode is selected.

In operating modes which provide high byte address recognition, the

FALC

® compares the high byte of a 2-byte address with the contents

of two individually programmable registers (RAH1, RAH2) and the

fixed values FE

H and FCH (broadcast address).

Depending on the result of this comparison, the following bit

combinations are possible:

00 = RAH2 has been recognized

01 = Broadcast address has been recognized

10 = RAH1 has been recognized C/R=0 (bit 1)

11 = RAH1 has been recognized C/R=1 (bit 1)

Note: If RAH1, RAH2 contain identical values, a match is indicated by

"10" or "11".

LA2

Low Byte Address Compare - HDLC Channel 2

Significant in HDLC modes only.

The low byte address of a 2-byte address field, or the single address

byte of a 1-byte address field is compared with two registers. (RAL1,

RAL2).

= RAL2 has been recognized

= RAL1 has been recognized

Signaling Status Register 3 (Read)

Value after reset: 00

XDOV3

Transmit Data Overflow - HDLC Channel 3

More than 32 bytes have been written to the XFIFO3.

This bit is reset

– by a transmitter reset command XRES or

– when all bytes in the accessible half of the XFIFO3 have been

moved in the inaccessible half.

XFW3

Transmit FIFO Write Enable - HDLC Channel 3

Data can be written to the XFIFO3.

SIS3

XDOV3

XFW3

XREP3

RLI3

CEC3

(9A)

PEB2256HT Datasheet(PDF) 326 Page - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 326 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL