PEB2256HT datasheet(422/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

422

2002-08-27

Receive DL-Bit Register 1 (Read)

RDL1(7:0)

Receive DL-Bit

Only valid if F12, F24 or F72 format is enabled.

The received FS/DL-Bits are shifted into this register. RDL10 is

received in frame 1 and RDL17 in frame 15, if F24 format is enabled.

RDL10 is received in frame 26 and RDL17 in frame 40, if F72 format

is enabled.

In F12 format the FS-Bits of a complete multiframe is stored in this

This register is updated with every receive multiframe begin interrupt

ISR0.RMB.

Receive DL-Bit Register 2 (Read)

RDL2(7:0)

Receive DL-Bit

Only valid if F24 or F72 format is enabled.

The received DL-Bits are shifted into this register. RDL20 is received

in frame 17 and RDL23 in frame 23, if F24 format is enabled. RDL20

is received in frame 42 and RDL27 in frame 56, if F72 format is

enabled.

This register is updated with every receive multiframe begin interrupt

ISR0.RMB.

RDL1

RDL17

RDL16

RDL15

RDL14

RDL13

RDL12

RDL11

RDL10

(5C)

RDL2

RDL27

RDL26

RDL25

RDL24

RDL23

RDL22

RDL21

RDL20

(5D)

PEB2256HT Datasheet(PDF) 422 Page - Infineon Technologies AG

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