PEB2256HT datasheet(420/490 Pages) INFINEON

Part #	PEB2256HT

Description	E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

PDF	490 Pages

Scroll/Zoom	100%

Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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420 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

420

2002-08-27

Bit Error Counter (Read)

BEC(15:0)

Bit Error Counter

If the PRBS monitor is enabled by LCR1.EPRM = 1 this 16-bit counter

is incremented with every received PRBS bit error in the PRBS

synchronous state FRS1.LLBAD = 1. The error counter does not roll

over.

During alarm simulation, the counter is incremented continuously with

every second received bit.

Clearing and updating the counter is done according to bit

FMR1.ECM.

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the PRBS bit error counter bit

DEC.DBEC has to be set. With the rising edge of this bit updating the

buffer is stopped and the error counter is reset. Bit DEC.DBEC is

automatically reset with reading the error counter high byte.

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then automatically reset. The latched error

counter state should be read within the next second.

BECL

BEC7

BEC0

(58)

BECH

BEC15

BEC8

(59)

PEB2256HT Datasheet(PDF) 420 Page - Infineon Technologies AG