PEB2256HT datasheet(417/490 Pages) INFINEON

417 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

417

2002-08-27

Code Violation Counter (Read)

CV(15:0)

Code Violations

No function if NRZ or CMI code has been enabled.

If the B8ZS code (bit FMR0.RC(1:0) = 11) is selected, the 16-bit

counter is incremented by detecting violations which are not due to

zero substitution. If FMR2.EXZE is set, additionally excessive zero

strings (more than 7 contiguous zeros) are detected and counted.

If simple AMI coding is enabled (FMR0.RC0/1 = 10) all bipolar

violations are counted. If FMR2.EXZE is set, additionally excessive

zero strings (more than 15 contiguous zeros) are detected and

counted. The error counter does not roll over.

During alarm simulation, the counter is incremented continuously with

every second received bit.

Clearing and updating the counter is done according to bit

FMR1.ECM.

If this bit is reset the error counter is permanently updated in the

buffer. For correct read access of the error counter bit DEC.DCVC

has to be set. With the rising edge of this bit updating the buffer is

stopped and the error counter is reset. Bit DEC.DCVC is

automatically reset with reading the error counter high byte.

If FMR1.ECM is set every second (interrupt ISR3.SEC) the error

counter is latched and then automatically reset. The latched error

counter state should be read within the next second.

CVCL

CV7

CV0

(52)

CVCH

CV15

CV8

(53)

PEB2256HT Datasheet(PDF) 417 Page - Infineon Technologies AG