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PEB2256HT Datasheet(PDF) 413 Page - Infineon Technologies AG

Part # PEB2256HT
Description  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT Datasheet(HTML) 413 Page - Infineon Technologies AG

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FALC56 V1.2
PEB 2256
T1/J1 Registers
Data Sheet
413
2002-08-27
Framer Receive Status Register 1 (Read)
EXZD
Excessive Zeros Detected
Significant
only
if
excessive
zeros
detection
is
enabled
(FMR2.EXZE = 1).
Set after detecting of more than 7 (B8ZS code) or more than 15 (AMI
code) contiguous zeros in the received bit stream. This bit is cleared
on read.
PDEN
Pulse-Density Violation Detected
The pulse-density of the received data stream is below the
requirement defined by ANSI T1. 403 or more than 14 consecutive
zeros are detected. With the violation of the pulse-density this bit is
set and remains active until the pulse-density requirement is fulfilled
for 23 consecutive "1"-pulses.
Additionally an interrupt status ISR0.PDEN is generated with the
rising edge of PDEN.
LLBDD
Line Loop-Back Deactivation Signal Detected
This bit is set in case of the LLB deactivate signal is detected and then
received over a period of more than 33,16 ms with a bit error rate less
than 10
-2. The bit remains set as long as the bit error rate does not
exceed 10
-2.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation.
Any change of this bit causes an LLBSC interrupt.
LLBAD
Line Loop-Back Activation Signal Detected/PRBS Status
Depending on bit LCR1.EPRM the source of this status bit changed.
LCR1.EPRM = 0: This bit is set in case of the LLB activate signal is
detected and then received over a period of more than 33,16 ms with
a bit error rate less than 10
-2. The bit remains set as long as the bit
error rate does not exceed 10
-2.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation.
Any change of this bit causes an LLBSC interrupt.
70
FRS1
EXZD
PDEN
LLBDD
LLBAD
XLS
XLO
(4D)



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