PEB2256HT datasheet(411/490 Pages) INFINEON

411 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

411

2002-08-27

Framer Receive Status Register 0 (Read)

LOS

Loss-of-Signal (Red Alarm)

Detection:

This bit is set when the incoming signal has “no transitions“ (analog

interface) or logical zeros (digital interface) in a time interval of T

consecutive pulses, where T is programmable by PCD register:

Total account of consecutive pulses: 16 < T < 4096.

Analog interface: The receive signal level where “no transition” is

declared is defined by the programmed value of LIM1.RIL(2:0).

Recovery:

Analog interface: The bit is reset in short-haul mode when the

incoming signal has transitions with signal levels greater than the

programmed receive input level (LIM1.RIL(2:0)) for at least M pulse

periods defined by register PCR in the PCD time interval. In long-haul

mode additionally bit RES.6 must be set for at least 250 µs.

Digital interface: The bit is reset when the incoming data stream

contains at least M ones defined by register PCR in the PCD time

interval.

With the rising edge of this bit an interrupt status bit (ISR2.LOS) is set.

For additionally recovery conditions refer also to register LIM2.LOS1.

The bit is set during alarm simulation and reset if FRS2.ESC = 0, 3,

4, 6,7 and no alarm condition exists.

AIS

Alarm Indication Signal (Blue Alarm)

This bit is set when the conditions defined by bit FMR4.AIS3 are

detected. The flag stays active for at least one multiframe.

With the rising edge of this bit an interrupt status bit (ISR2.AIS) is set.

It is reset with the beginning of the next following multiframe if no

alarm condition is detected.

The bit is set during alarm simulation and reset if FRS2.ESC = 0, 3,

4, 7 and no alarm condition exists.

FRS0

LOS

AIS

LFA

RRA

LMFA

FSRF

(4C)

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