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PEB2256HT Datasheet(PDF) 415 Page - Infineon Technologies AG |
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PEB2256HT Datasheet(HTML) 415 Page - Infineon Technologies AG |
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415 / 490 page  FALC56 V1.2 PEB 2256 T1/J1 Registers Data Sheet 415 2002-08-27 Framer Receive Status Register 2 (Read) ESC(2:0) Error Simulation Counter This three-bit counter is incremented by setting bit FMR0.SIM. The state of the counter determines the function to be tested. For complete checking of the alarm indications, eight simulation steps are necessary (FRS2.ESC = 0 after a complete simulation). 70 FRS2 ESC2 ESC1 ESC0 (4E) Table 68 Alarm Simulation States Tested Alarms ESC(2:0) = 012 34567 LFA ×× LMFA ×× RRA (bit2 = 0) × RRA (S-bit frame 12) × RRA (DL-pattern) × LOS 1) 1) only active during FMR0.SIM = 1 ×× × EBC 2) (F12,F72) 2) FEC is counting +2 while EBC is counting +1 if the framer is in synchronous state; if asynchronous in state 2 but synchronous in state 6, counters are incremented during state 6 ×(×) EBC 2) (only ESF) ×× × (×) AIS 1) ×× ×× FEC 2) ×(×) CVC ×× × CEC (only ESF) ×× ×× RSP × RSN × XSP × XSN × BEC 1) ×× × COEC ×× |
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