PEB2256HT datasheet(414/490 Pages) INFINEON

414 / 490 page

FALC56 V1.2

PEB 2256

T1/J1 Registers

Data Sheet

414

2002-08-27

PRBS Status

LCR1.EPRM = 1: The current status of the PRBS synchronizer is

indicated in this bit. It is set high if the synchronous state is reached

even in the presence of a bit error rate of up to 10

-3. A data stream

containing all zeros or all ones with/without framing bits is also a valid

pseudo-random binary sequence.

XLS

Transmit Line Short

Significant only if the ternary line interface is selected by

LIM1.DRS = 0.

0 =

Normal operation. No short is detected.

1 =

The XL1 and XL2 are shortened for at least 3 pulses. As a

reaction of the short the pins XL1 and XL2 are automatically

forced into a high-impedance state if bit XPM2.DAXLT is reset.

After 128 consecutive pulse periods the outputs XL1/2 are

activated again and the internal transmit current limiter is

checked. If a short between XL1/2 is still further active the

outputs XL1/2 are in high-impedance state again. When the

short disappears pins XL1/2 are activated automatically and

this bit is reset. With any change of this bit an interrupt

ISR1.XLSC is generated. In case of XPM2.XLT is set this bit is

frozen.

XLO

Transmit Line Open

0 =

Normal operation

1 =

This bit is set if at least 32 consecutive zeros were sent on pins

XL1/XL2 or XDOP/XDON. This bit is reset with the first

transmitted pulse. With the rising edge of this bit an interrupt

ISR1.XLSC is set. In case of XPM2.XLT is set this bit is frozen.

PEB2256HT Datasheet(PDF) 414 Page - Infineon Technologies AG